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    Hetero-bimos injection process for non-volatile flash memory
    142.
    发明授权
    Hetero-bimos injection process for non-volatile flash memory 有权
    非易失性闪存的异质双向注射工艺

    公开(公告)号：US07598560B2

    公开(公告)日：2009-10-06

    申请号：US11731162

    申请日：2007-03-30

    Applicant: Jack T. Kavalieros ,  Suman Datta ,  Robert S. Chau ,  David L. Kencke

    Inventor： Jack T. Kavalieros ,  Suman Datta ,  Robert S. Chau ,  David L. Kencke

    IPC: H01L29/76 ,  H01L29/788

    CPC classification number: H01L21/8249 ,  H01L21/28273 ,  H01L27/0705 ,  H01L29/0821 ,  H01L29/66825 ,  H01L29/73 ,  H01L29/7606 ,  H01L29/7881

    Abstract: A hetero-BiMOS injection system comprises a MOSFET transistor formed on a substrate and a hetero-bipolar transistor formed within the substrate. The bipolar transistor can be used to inject charge carriers into a floating gate of the MOSFET transistor. This is done by operating the MOSFET transistor to form an inversion layer in its channel region and operating the bipolar transistor to drive minority charge carriers from the substrate into a floating gate of the MOSFET transistor. The substrate provides a silicon emitter and a silicon germanium containing base for the bipolar transistor. The inversion layer provides a silicon collector for the bipolar transistor.

    Abstract translation: 异质BiMOS注入系统包括形成在衬底上的MOSFET晶体管和形成在衬底内的异质双极晶体管。 双极晶体管可用于将电荷载流子注入MOSFET晶体管的浮置栅极。 这通过操作MOSFET晶体管在其沟道区域中形成反型层并且操作双极晶体管来驱动少数电荷载体从衬底驱动到MOSFET晶体管的浮置栅极。 衬底为双极晶体管提供硅发射极和含硅锗基底。 反型层为双极晶体管提供硅集电极。

    Tri-gate patterning using dual layer gate stack
    143.
    发明申请
    Tri-gate patterning using dual layer gate stack 有权
    使用双层栅极堆叠的三栅极图案化

    公开(公告)号：US20090170267A1

    公开(公告)日：2009-07-02

    申请号：US12006047

    申请日：2007-12-28

    Applicant: Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    Inventor： Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    IPC: H01L21/336

    CPC classification number: H01L21/823821 ,  H01L29/66795 ,  H01L29/785

    Abstract: In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A ploysilicon layer is formed over the silicon germanium layer and is polished. The ploysilicon layer over the first work function metal layer is thicker than the ploysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the ploysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.

    Abstract translation: 通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。 在衬底上形成高介电常数层。 在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。 在第一和第二功函数金属层上形成硅锗层。 在硅锗层上方形成硅层，并进行抛光。 第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。 硬掩模被图案化并用于蚀刻合金层和硅锗层以产生栅极堆叠。 硅锗层的蚀刻速率比第一功函数金属层更快。

    INDEPENDENT GATE ELECTRODES TO INCREASE READ STABILITY IN MULTI-GATE TRANSISTORS
    144.
    发明申请
    INDEPENDENT GATE ELECTRODES TO INCREASE READ STABILITY IN MULTI-GATE TRANSISTORS 审中-公开
    独立门电极增加多栅极晶体管的读稳定性

    公开(公告)号：US20090166743A1

    公开(公告)日：2009-07-02

    申请号：US11964633

    申请日：2007-12-26

    Applicant: Ravi Pillarisetty ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

    Inventor： Ravi Pillarisetty ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Robert S. Chau

    IPC: H01L29/78 ,  H01L21/28

    CPC classification number: H01L27/1104 ,  H01L27/11 ,  H01L29/785

    Abstract: Independent gate electrodes for multi-gate transistors are generally described. In one example, an apparatus includes a semiconductor fin, one or more multi-gate pull down (PD) gate stacks coupled with the semiconductor fin, the one or more PD gate stacks including a PD gate electrode, and one or more multi-gate pass gate (PG) gate stacks coupled with the semiconductor fin, the one or more PG gate stacks including a PG gate electrode, the PG gate electrode having a greater threshold voltage than the PD gate electrode.

    Abstract translation: 通常描述用于多栅极晶体管的独立栅电极。 在一个示例中，装置包括半导体鳍片，与半导体鳍片耦合的一个或多个多栅极下拉（PD）栅极叠层，所述一个或多个PD栅极堆叠包括PD栅极电极和一个或多个多栅极 所述PG栅极堆叠与所述半导体鳍片耦合，所述一个或多个PG栅极堆叠包括PG栅极电极，所述PG栅电极具有比所述PD栅电极更大的阈值电压。

    Forming a type I heterostructure in a group IV semiconductor
    146.
    发明授权
    Forming a type I heterostructure in a group IV semiconductor 有权
    在IV族半导体中形成I型异质结构

    公开(公告)号：US07435987B1

    公开(公告)日：2008-10-14

    申请号：US11728890

    申请日：2007-03-27

    Applicant: Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

    Inventor： Chi On Chui ,  Prashant Majhi ,  Wilman Tsai ,  Jack T. Kavalieros

    IPC: H01L31/0328

    CPC classification number: H01L29/155 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/7782

    Abstract: In one embodiment, the present invention includes a method for forming a transistor that includes forming a first buffer layer of silicon germanium tin (SiGe(Sn)) on a silicon (Si) substrate, forming a barrier layer on the first buffer layer, the barrier layer comprising silicon germanium (Si1−xGex), and forming a quantum well (QW) layer on the barrier layer including a lower QW barrier layer formed of silicon germanium carbon (Si1−yGey(C)), a strained QW channel layer formed of germanium on the lower QW layer, and an upper QW barrier layer on the strained QW channel layer formed of Si1−zGez(C). Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于形成晶体管的方法，该晶体管包括在硅（Si）衬底上形成硅锗锡（SiGe（Sn））的第一缓冲层，在第一缓冲层上形成阻挡层， 阻挡层，其包含硅锗（Si 1-x N x Ge x Si x Ga y），并且在阻挡层上形成量子阱（QW）层，其包括由硅形成的下部QW势垒层 锗碳（Si 1-y）Ge（C）），由QW层上的锗形成的应变QW沟道层和上QW沟道层 应变QW沟道层由Si 1-z≡Z（C）形成。 描述和要求保护其他实施例。

    Transistor having tensile strained channel and system including same
    148.
    发明申请
    Transistor having tensile strained channel and system including same 有权
    具有拉伸应变通道的晶体管和包括其的系统

    公开(公告)号：US20080237636A1

    公开(公告)日：2008-10-02

    申请号：US11729564

    申请日：2007-03-29

    Applicant: Been-Yih Jin ,  Robert S. Chau ,  Suman Datta ,  Jack T. Kavalieros ,  Marko Radosavlievic

    Inventor： Been-Yih Jin ,  Robert S. Chau ,  Suman Datta ,  Jack T. Kavalieros ,  Marko Radosavlievic

    IPC: H01L29/778

    CPC classification number: H01L29/1054 ,  H01L29/517 ,  H01L29/7787 ,  H01L29/7843 ,  H01L29/7851

    Abstract: A transistor structure and a system including the transistor structure. The transistor structure comprises: a substrate including a first layer comprising a first crystalline material; a tensile strained channel formed on a surface of the first layer and comprising a second crystalline material having a lattice spacing that is smaller than a lattice spacing of the first crystalline material; a metal gate on the substrate; a pair of sidewall spacers on opposite sides of the metal gate; and a source region and a drain region on opposite sides of the metal gate adjacent a corresponding one of the sidewall spacers.

    Abstract translation: 晶体管结构和包括晶体管结构的系统。 晶体管结构包括：衬底，其包括包含第一晶体材料的第一层; 形成在所述第一层的表面上的拉伸应变通道，并且包括晶格间距小于所述第一结晶材料的晶格间距的第二结晶材料; 基板上的金属栅极; 在金属门的相对侧上的一对侧壁间隔件; 以及在金属栅极的与相应的一个侧壁间隔物相邻的相对侧上的源极区域和漏极区域。

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