公开(公告)号：US20170363721A1

公开(公告)日：2017-12-21

申请号：US15624346

申请日：2017-06-15

Applicant: STMicroelectronics, Inc.

Inventor： Xiaoyong Yang ,  Rui Xiao

IPC: G01S7/48 ,  G01S7/481 ,  G01S17/87 ,  G01S17/89

CPC classification number: G01S7/4816 ,  G01S7/4802 ,  G01S7/4863 ,  G01S17/10 ,  G01S17/89 ,  G07C9/00 ,  G07C9/00071

Abstract: A user identification based control system includes a time of flight ranging sensor configured to sense a distance to a person, where the time of flight ranging sensor is positioned so the sensed distance is a function of a height of the person. Processing circuitry is coupled to the time of flight ranging sensor and configured to identify the person based upon sensed distance and to generate control signals to control peripheral components based upon the identity of the person. The time of flight ranging sensor may also be used to sense speed of the person for identification purposes. In general, the time of flight ranging sensor is positioned a known height over a surface on which the person is present, such as in the doorway or on a ceiling of a room.

公开(公告)号：US09842794B2

公开(公告)日：2017-12-12

申请号：US14945291

申请日：2015-11-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Ela Mia Cadag ,  Jefferson Talledo

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/4952 ,  H01L21/4828 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81002 ,  H01L2224/81986 ,  H01L2224/83002 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/83986 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/13099 ,  H01L2924/00

Abstract: One or more embodiments are directed to semiconductor packages having an integrated heatsink and methods of forming same. In one embodiment, a package includes a plurality of leads that support and enclose periphery portions of the semiconductor die. The leads have first and second, opposing surfaces that form outer surfaces of the package. The first surface of the leads may form a heatsink and the second surface of the leads form lands of the package for coupling to another device, substrate, or board. The package includes encapsulation material that surrounds the semiconductor die and located between upper portions of the leads. The package further includes a back filling material (or insulating material) that is below the semiconductor die and between lower portions of the leads.

公开(公告)号：US09841341B2

公开(公告)日：2017-12-12

申请号：US14861648

申请日：2015-09-22

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS, INC.

Inventor： Fulvio Vittorio Fontana ,  Jefferson Talledo

IPC: H01L21/50 ,  H01L23/498 ,  G01L19/14 ,  B81B7/00 ,  B81C1/00 ,  H01L23/057 ,  H01L23/495

CPC classification number: G01L19/148 ,  B81B7/0045 ,  B81C1/00325 ,  H01L21/50 ,  H01L23/057 ,  H01L23/49575 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014

Abstract: A surface mounting device has one body of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals. The base region has a Young's modulus lower than 5 MPa. For forming the device, the body is attached to a supporting frame including contact terminals and a die pad, separated by cavities; bonding wires are soldered to the body and to the contact terminals; an elastic material is molded so as to surround at least in part lateral sides of the body, fill the cavities of the supporting frame and cover the ends of the bonding wires on the contact terminals; and a cap is fixed to the base region. The die pad is then etched away.

公开(公告)号：US09837320B2

公开(公告)日：2017-12-05

申请号：US15582962

申请日：2017-05-01

Applicant: STMicroelectronics, Inc.

Inventor： John C. Pritiskutch ,  Richard Hildenbrandt

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L21/266 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L21/823493 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/7827

Abstract: First and second transistors with different electrical characteristics are supported by a substrate having a first-type dopant. The first transistor includes a well region within the substrate having the first-type dopant, a first body region within the well region having a second-type dopant and a first source region within the first body region and laterally offset from the well region by a first channel. The second transistor includes a second body region within the semiconductor substrate layer having the second-type dopant and a second source region within the second body region and laterally offset from material of the substrate by a second channel having a length greater than the length of the first channel. A gate region extends over portions of the first and second body regions for the first and second channels, respectively.

公开(公告)号：US20170345935A1

公开(公告)日：2017-11-30

申请号：US15677855

申请日：2017-08-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165 ,  H01L21/84 ,  H01L29/16 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092 ,  H01L29/786 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78654

Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.

公开(公告)号：US09826434B2

公开(公告)日：2017-11-21

申请号：US13710321

申请日：2012-12-10

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: H04W28/20 ,  H04W28/22

CPC classification number: H04W28/20

Abstract: Methods and systems are disclosed for the operation of wireless communication networks, in which communication channels can have possibly overlapping bandwidths of different sizes, including sensor networks operating by the IEEE 802.11ah standard. A first method of signaling to negotiate the channel bandwidth conveys the needed information in the SIG field of the PPDUs of duplicate RTS/CTS frames, and uses the SIG field of PPDUs of duplicated data, control and management frames to perform transmit opportunity protection. A second method of signaling to negotiate the channel bandwidth conveys the needed information in the scrambling sequence field of PPDUs of duplicate RTS, and uses the scrambling sequence field of PPDUs of duplicated data, control and management frames to perform transmit opportunity protection.

公开(公告)号：US09818930B2

公开(公告)日：2017-11-14

申请号：US14938432

申请日：2015-11-11

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L41/332 ,  B23P15/00 ,  C03C25/00 ,  C23F1/00 ,  H01L41/09

CPC classification number: H01L41/332 ,  H01L41/0973

Abstract: A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.

公开(公告)号：US09801114B2

公开(公告)日：2017-10-24

申请号：US14843679

申请日：2015-09-02

Applicant: STMicroelectronics, Inc.

Inventor： Oleg Logvinov ,  Aidan Cully ,  James D. Allen

IPC: H04W4/00 ,  H04W40/08 ,  H04W52/02 ,  H04W52/46 ,  H04W40/10 ,  H04L12/801 ,  H04L12/24 ,  H04L12/26

CPC classification number: H04W40/08 ,  H04L41/0833 ,  H04L43/08 ,  H04L43/0876 ,  H04L47/13 ,  H04W40/10 ,  H04W52/0219 ,  H04W52/46 ,  Y02D30/20 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/162 ,  Y02D70/23 ,  Y02D70/324 ,  Y02D70/326

Abstract: In accordance with an embodiment, a network device includes a network controller and at least one network interface coupled to the network controller that includes at least one media access control (MAC) device configured to be coupled to at least one physical layer interface (PHY). The network controller may be configured to determine a network path comprising the at least one network interface that has a lowest power consumption and minimum security attributes of available media types coupled to the at least one PHY.

公开(公告)号：US09773885B2

公开(公告)日：2017-09-26

申请号：US15471733

申请日：2017-03-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Andrew M. Greene ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

公开(公告)号：US09768299B2

公开(公告)日：2017-09-19

申请号：US14977077

申请日：2015-12-21

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78654

Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.