公开(公告)号：US20160146692A1

公开(公告)日：2016-05-26

申请号：US14861648

申请日：2015-09-22

申请人： STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS, INC.

发明人： Fulvio Vittorio Fontana ,  Jefferson Talledo

IPC分类号： G01L19/14

CPC分类号： G01L19/148 ,  B81B7/0045 ,  B81C1/00325 ,  H01L21/50 ,  H01L23/057 ,  H01L23/49575 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014

摘要： A surface mounting device has one body of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals. The base region has a Young's modulus lower than 5 MPa. For forming the device, the body is attached to a supporting frame including contact terminals and a die pad, separated by cavities; bonding wires are soldered to the body and to the contact terminals; an elastic material is molded so as to surround at least in part lateral sides of the body, fill the cavities of the supporting frame and cover the ends of the bonding wires on the contact terminals; and a cap is fixed to the base region. The die pad is then etched away.

摘要翻译： 表面安装装置具有一个诸如ASIC的半导体材料，以及围绕该主体的封装。 该包装具有承载本体的基部区域，盖子和接触端子。 基部区域的杨氏模量低于5MPa。 为了形成装置，主体附接到支撑框架，该支撑框架包括由空腔分开的接触端子和模片垫; 接合线焊接到主体和接触端子; 将弹性材料模制成至少围绕主体的侧面，填充支撑框架的空腔并覆盖接触端子上的接合线的端部; 并且帽固定到基部区域。 然后蚀刻掉芯片焊盘。

公开(公告)号：US09841341B2

公开(公告)日：2017-12-12

申请号：US14861648

申请日：2015-09-22

申请人： STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS, INC.

发明人： Fulvio Vittorio Fontana ,  Jefferson Talledo

IPC分类号： H01L21/50 ,  H01L23/498 ,  G01L19/14 ,  B81B7/00 ,  B81C1/00 ,  H01L23/057 ,  H01L23/495

CPC分类号： G01L19/148 ,  B81B7/0045 ,  B81C1/00325 ,  H01L21/50 ,  H01L23/057 ,  H01L23/49575 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014

摘要： A surface mounting device has one body of semiconductor material such as an ASIC, and a package surrounding the body. The package has a base region carrying the body, a cap and contact terminals. The base region has a Young's modulus lower than 5 MPa. For forming the device, the body is attached to a supporting frame including contact terminals and a die pad, separated by cavities; bonding wires are soldered to the body and to the contact terminals; an elastic material is molded so as to surround at least in part lateral sides of the body, fill the cavities of the supporting frame and cover the ends of the bonding wires on the contact terminals; and a cap is fixed to the base region. The die pad is then etched away.

公开(公告)号：US11948868B2

公开(公告)日：2024-04-02

申请号：US17537318

申请日：2021-11-29

申请人： STMICROELECTRONICS, INC.

发明人： Jefferson Talledo

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49548 ,  H01L21/4828 ,  H01L23/3142 ,  H01L23/49513 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48175 ,  H01L2224/73265

摘要： Generally described, one or more embodiments are directed to a leadframe package having a plurality of leads, a die pad, a semiconductor die coupled to the die pad, and encapsulation material. An inner portion of the die pad includes a perimeter portion that includes a plurality of protrusions that are spaced apart from each other. The protrusions aid in locking the die pad in the encapsulation material. The plurality of leads includes upper portions and base portions. The base portion of the plurality of leads are offset (or staggered) relative to the plurality of protrusions of the die pad. In particular, the base portions extend longitudinally toward the die pad and are located between respective protrusions. The upper portions of the leads include lead locks that extend beyond the base portions in a direction of adjacent leads. The lead locks and the protrusion in the die pad aid in locking the leads and the die pad in the encapsulation material.

公开(公告)号：US10957634B2

公开(公告)日：2021-03-23

申请号：US16800923

申请日：2020-02-25

申请人： STMicroelectronics, Inc.

发明人： Rennier Rodriguez ,  Aiza Marie Agudon ,  Jefferson Talledo ,  Moonlord Manalo ,  Ela Mia Cadag ,  Rammil Seguido

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

摘要： The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US09768126B2

公开(公告)日：2017-09-19

申请号：US14721831

申请日：2015-05-26

申请人： STMicroelectronics, Inc.

发明人： Jefferson Talledo ,  Godfrey Dimayuga

IPC分类号： G01R31/20 ,  H01L23/00 ,  H01L23/13 ,  H01L25/10 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L23/562 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/35 ,  H01L2924/3511

摘要： One or more embodiments are directed to semiconductor packages, including stacked packages, with one or more cantilever pads. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.

公开(公告)号：US09627224B2

公开(公告)日：2017-04-18

申请号：US14672664

申请日：2015-03-30

申请人： STMICROELECTRONICS, INC.

发明人： Godfrey Dimayuga ,  Jefferson Talledo

IPC分类号： H01L23/48 ,  H01L21/48 ,  H01L23/498 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/486 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board.

公开(公告)号：US11699667B2

公开(公告)日：2023-07-11

申请号：US17306363

申请日：2021-05-03

申请人： STMICROELECTRONICS, INC.

发明人： Jefferson Talledo

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L23/562 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49551

摘要： A leadframe having extensions around an outer edge of a die pad are disclosed. More specifically, leadframes are created with a flange formed at the outer edge of the die pad and extending away from the die pad. The flange is bent, such that it is positioned at an angle with respect to the die pad. Leadframes are also created with anchoring posts formed adjacent the outer edge of the die pad and extending away from the die pad. The anchoring posts have a central thickness that is less than a thickness of first and second portions opposite the central portion. When the leadframe is incorporated into a package, molding compound completely surrounds each flange or anchoring post, which increases the bond strength between the leadframe and the molding compound due to increased contact area. The net result is a reduced possibility of delamination at edges of the die pad.

公开(公告)号：US11227817B2

公开(公告)日：2022-01-18

申请号：US16707823

申请日：2019-12-09

申请人： STMICROELECTRONICS, INC.

发明人： Jefferson Talledo

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

摘要： Generally described, one or more embodiments are directed to a leadframe package having a plurality of leads, a die pad, a semiconductor die coupled to the die pad, and encapsulation material. An inner portion of the die pad includes a perimeter portion that includes a plurality of protrusions that are spaced apart from each other. The protrusions aid in locking the die pad in the encapsulation material. The plurality of leads includes upper portions and base portions. The base portion of the plurality of leads are offset (or staggered) relative to the plurality of protrusions of the die pad. In particular, the base portions extend longitudinally toward the die pad and are located between respective protrusions. The upper portions of the leads include lead locks that extend beyond the base portions in a direction of adjacent leads. The lead locks and the protrusion in the die pad aid in locking the leads and the die pad in the encapsulation material.

公开(公告)号：US10388594B2

公开(公告)日：2019-08-20

申请号：US15636533

申请日：2017-06-28

申请人： STMICROELECTRONICS, INC.

发明人： Frederick Ray Gomez ,  Tito Mangaoang, Jr. ,  Jefferson Talledo

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/60 ,  H01L23/495

摘要： According to principles of the disclosure as explained herein, selected leads are electrically connected through metal strips to the lead frame until the end of the manufacturing process. The lead frame is grounded through the manufacturing process to prevent any ESD event from causing damage to the protected leads. In the final singulation step, the leads are electrically isolated from each other and from the lead frame, thus maintaining protection from a potential ESD event up until the final package singulation step.

公开(公告)号：US20190096789A1

公开(公告)日：2019-03-28

申请号：US16203217

申请日：2018-11-28

申请人： STMicroelectronics, Inc.

发明人： Jefferson Talledo

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/495

摘要： The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array.