公开(公告)号：US08241995B2

公开(公告)日：2012-08-14

申请号：US11532599

申请日：2006-09-18

申请人： Kuan-Neng Chen ,  Bruce K. Furman ,  Sampath Purushothaman ,  David L. Rath ,  Anna W. Topol ,  Cornelia K. Tsang

发明人： Kuan-Neng Chen ,  Bruce K. Furman ,  Sampath Purushothaman ,  David L. Rath ,  Anna W. Topol ,  Cornelia K. Tsang

IPC分类号： H01L21/30

CPC分类号： H01L24/05 ,  B23K20/023 ,  B23K20/233 ,  B23K20/24 ,  B23K2101/42 ,  H01L24/03 ,  H01L24/08 ,  H01L24/12 ,  H01L24/80 ,  H01L2224/0381 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80203 ,  H01L2224/80345 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T428/24479 ,  Y10T428/24521 ,  Y10T428/24545 ,  Y10T428/24612 ,  Y10T428/31678 ,  H01L2924/00012 ,  H01L2924/0001 ,  H01L2924/00

摘要： Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric is disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.

摘要翻译： 公开了包括金属介电图案在衬底上的金属与在电介质上方凸起的金属的结合。 一种方法包括在其表面上提供具有金属 - 电介质图案的第一基板; 提供在其表面上具有金属 - 电介质图案的第二基板; 执行导致金属在电介质上方升高的过程; 清洗金属; 以及将所述第一基板接合到所述第二基板。 还公开了相关的结构。 凸起金属的结合提供了强大的粘合介质，以及良好的电气和热连接，能够创建具有增强功能的三维集成结构。

公开(公告)号：US20110111560A1

公开(公告)日：2011-05-12

申请号：US12615175

申请日：2009-11-09

申请人： Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongging Yu

发明人： Sampath Purushothaman ,  Mary E. Rothwell ,  Ghavam Ghavami Shahidi ,  Roy Rongging Yu

IPC分类号： H01L21/50

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06593

摘要： A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

摘要翻译： 三维器件堆叠结构包括两个或更多个有源器件和互连层，其通过衬底通孔进一步连接在一起。 形成三维器件堆叠结构的方法包括对准，通过层压粘接，变薄和后变薄处理。 通孔特征使得能够通过层压工艺和任何后续工艺步骤保持对准，从而与现有技术相比实现机械上更坚固的堆叠结构。

公开(公告)号：US07880305B2

公开(公告)日：2011-02-01

申请号：US10290049

申请日：2002-11-07

申请人： Yu-Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

发明人： Yu-Ting Cheng ,  Sherif A. Goma ,  John Harold Magerlein ,  Sampath Purushothaman ,  Carlos Juan Sambucetti ,  George Frederick Walker

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/422 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K2201/09563 ,  H05K2201/10378 ,  H05K2203/025 ,  H01L2924/00

摘要： The invention is the technology of providing a packaging intermediate product that can serve as an interface substrate that is to be positioned between different circuitry types where the dimensions are approaching the sub 100 micrometer range. The invention involves a dielectric wafer structure where the first and second area surfaces of the wafer are separated by a distance that is of the order of the electrical via design length, and an array of spaced vias through the wafer arranged with each via filled with metal surrounded by a chemical metal deposition promoting layer with each via terminating flush with a wafer surface. The wafer structure is achieved by forming an array of blind via openings through the first surface of the dielectric wafer to a depth approaching the via design length, lining the walls for adhesion enhancement, filling the blind via openings completely with a chemically deposited metal, removing material at the first wafer surface thereby planarizing the filled vias, and removing material at the second wafer surface thereby exposing the vias at the design length.

摘要翻译： 本发明是提供一种包装中间产品的技术，该包装中间产品可以用作界面基底，该界面基底将位于尺寸接近亚100微米范围的不同电路类型之间。 本发明涉及一种电介质晶片结构，其中晶片的第一和第二区域表面被隔开距离为电通孔设计长度的数量级，并且通过晶片布置的间隔开的通孔阵列，每个通孔填充有金属 被化学金属沉积促进层围绕，每个通孔终止与晶片表面齐平。 晶片结构通过形成通过介电晶片的第一表面的盲孔通孔的阵列达到接近通孔设计长度的深度来实现，衬里壁用于粘附增强，用化学沉积的金属完全填充盲孔通孔，去除 材料，从而使填充的通孔平坦化，以及在第二晶片表面移除材料，从而在设计长度处露出通孔。

公开(公告)号：US07855101B2

公开(公告)日：2010-12-21

申请号：US12544226

申请日：2009-08-20

申请人： Bruce K. Furman ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Anna Topol

发明人： Bruce K. Furman ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Anna Topol

IPC分类号： H01L21/50

CPC分类号： H01L21/768 ,  H01L21/2007 ,  H01L21/84 ,  H01L23/3735 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.

摘要翻译： 提供了一种用于半导体部件的结构，其具有通过其它有源，无源和互连部件夹在两侧的器件层。 使用晶片级层传输过程来创建具有附加功能增强的平面（2D）IC结构。

公开(公告)号：US07781332B2

公开(公告)日：2010-08-24

申请号：US11857805

申请日：2007-09-19

申请人： John C. Arnold ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga K. Shobha ,  Terry A. Spooner

发明人： John C. Arnold ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Hosadurga K. Shobha ,  Terry A. Spooner

IPC分类号： H01L21/4763 ,  H01L21/302

CPC分类号： H01L23/5329 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

摘要： Plasma damage in ultra low k dielectric materials during formation of a dual damascene metal interconnect structure is reduced by providing a protective spacer on sidewalls of a line trench. A densified trench bottom region may be additionally formed directly beneath an exposed horizontal surface of the line trench. The protective spacer and/or the densified trench bottom region protects an ultra low k intermetal dielectric layer from plasma damage during a plasma strip process that is used to remove a disposable via fill plug employed in the dual damascene metal interconnect structure.

摘要翻译： 在形成双镶嵌金属互连结构的超低k电介质材料中的等离子体损伤通过在管线沟槽的侧壁上设置保护隔离物来减少。 致密沟槽底部区域可以直接附加地形成在线沟槽的暴露的水平表面下方。 保护间隔物和/或致密的沟槽底部区域在用于去除在双镶嵌金属互连结构中使用的一次性通孔填充塞的等离子体条带过程中保护超低k金属间介电层免受等离子体损伤。

公开(公告)号：US20090305460A1

公开(公告)日：2009-12-10

申请号：US12544964

申请日：2009-08-20

申请人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

发明人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

IPC分类号： H01L21/06

CPC分类号： H01L45/06 ,  H01L28/20 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

摘要： Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; a heater over the first dielectric layer; an air gap separating at least a portion of the heater from the first dielectric layer; an isolation layer over the first dielectric layer covering at least a portion of the heater; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.

摘要翻译： 提供可编程的器件及其制造方法。 在一个方面，提供了可编程通路装置。 可编程通孔装置包括第一介电层; 第一介电层上的加热器; 将所述加热器的至少一部分与所述第一介电层分开的气隙; 覆盖所述加热器的至少一部分的所述第一介电层上的隔离层; 在所述隔离层的与所述第一介电层相对的一侧上的覆盖层; 至少一个可编程通道，其延伸穿过所述封盖层和所述隔离层的至少一部分并与所述加热器接触，所述可编程通孔包括至少一个相变材料; 可编程通孔上的导电盖; 在覆盖层的与隔离层相对的一侧上的第二电介质层; 第一导电通孔和第二导电通孔，每个延伸穿过第二介电层，封盖层和至少一部分隔离层并与加热器接触; 以及延伸穿过所述第二介电层并与所述导电盖接触的第三导电通孔。

公开(公告)号：US20090033360A1

公开(公告)日：2009-02-05

申请号：US11833354

申请日：2007-08-03

申请人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

发明人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

IPC分类号： H03K19/177 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L28/20 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

摘要： Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; a heater over the first dielectric layer; an air gap separating at least a portion of the heater from the first dielectric layer; an isolation layer over the first dielectric layer covering at least a portion of the heater; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.

摘要翻译： 提供可编程的器件及其制造方法。 在一个方面，提供了可编程通路装置。 可编程通孔装置包括第一介电层; 第一介电层上的加热器; 将所述加热器的至少一部分与所述第一介电层分开的气隙; 覆盖所述加热器的至少一部分的所述第一介电层上的隔离层; 在所述隔离层的与所述第一介电层相对的一侧上的覆盖层; 至少一个可编程通道，其延伸穿过所述封盖层和所述隔离层的至少一部分并与所述加热器接触，所述可编程通孔包括至少一个相变材料; 可编程通孔上的导电盖; 在覆盖层的与隔离层相对的一侧上的第二电介质层; 第一导电通孔和第二导电通孔，每个延伸穿过第二介电层，封盖层和至少一部分隔离层并与加热器接触; 以及延伸穿过所述第二介电层并与所述导电盖接触的第三导电通孔。

公开(公告)号：US20090033358A1

公开(公告)日：2009-02-05

申请号：US11833321

申请日：2007-08-03

申请人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

发明人： Kuan-Neng Chen ,  Lia Krusin-Elbaum ,  Dennis M. Newns ,  Sampath Purushothaman

IPC分类号： H01L45/00 ,  H03K19/177

CPC分类号： H01L28/65 ,  H01L28/20 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  Y10S977/754

摘要： Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; at least one isolation layer over the first dielectric layer; a heater within the isolation layer; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.

摘要翻译： 提供可编程的器件及其制造方法。 在一个方面，提供了可编程通路装置。 可编程通孔装置包括第一介电层; 在所述第一介电层上方的至少一个隔离层; 隔离层内的加热器; 在所述隔离层的与所述第一介电层相对的一侧上的覆盖层; 至少一个可编程通道，其延伸穿过所述封盖层和所述隔离层的至少一部分并与所述加热器接触，所述可编程通孔包括至少一个相变材料; 可编程通孔上的导电盖; 在覆盖层的与隔离层相对的一侧上的第二电介质层; 第一导电通孔和第二导电通孔，每个延伸穿过第二介电层，封盖层和至少一部分隔离层并与加热器接触; 以及延伸穿过所述第二介电层并与所述导电盖接触的第三导电通孔。

公开(公告)号：US20080277778A1

公开(公告)日：2008-11-13

申请号：US11746680

申请日：2007-05-10

申请人： Bruce K. Furman ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Anna Topol

发明人： Bruce K. Furman ,  Sampath Purushothaman ,  Muthumanickam Sankarapandian ,  Anna Topol

IPC分类号： H01L21/46 ,  H01L23/34

CPC分类号： H01L21/768 ,  H01L21/2007 ,  H01L21/84 ,  H01L23/3735 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.

摘要翻译： 提供了一种用于半导体部件的结构，其具有通过其它有源，无源和互连部件夹在两侧的器件层。 使用晶片级层传输过程来创建具有附加功能增强的平面（2D）IC结构。

公开(公告)号：US20060267208A1

公开(公告)日：2006-11-30

申请号：US11405283

申请日：2006-04-17

申请人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

发明人： Matthew Colburn ,  Timothy Dalton ,  Elbert Huang ,  Simon Karecki ,  Satya Nitta ,  Sampath Purushothaman ,  Katherine Saenger ,  Maheswaran Surendra

IPC分类号： H01L23/48 ,  H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form a closed air gap interconnect structure is described. A starting structure made of regions of a permanent support dielectric under the interconnect lines and surrounding interconnect vias with one or more sacrificial dielectrics present in the remaining portions of the interconnect structure, is capped with a dielectric barrier which is perforated using a stencil with a regular array of holes. The sacrificial dielectrics are then extracted through the holes in the dielectric barrier layer such that the interconnect lines are substantially surrounded by air except for the regions of the support dielectric under the lines. The holes in the cap layer are closed off by depositing a second barrier dielectric so that a closed air gap is formed. Several embodiments of this method and the resulting structures are described.

摘要翻译： 描述了形成闭合气隙互连结构的方法。 在互连线下方由永久支撑电介质的区域构成的起始结构和在互连结构的其余部分中存在的具有一个或多个牺牲电介质的周围的互连通孔被封装有电介质阻挡层，其使用具有规则的模板 孔阵列 然后通过电介质阻挡层中的孔提取牺牲电介质，使得互连线基本上被除了线下方的支撑电介质的区域之外的空气包围。 通过沉积第二阻挡电介质来封闭盖层中的孔，从而形成封闭的气隙。 描述该方法的几个实施例和所得到的结构。