公开(公告)号：US20230305744A1

公开(公告)日：2023-09-28

申请号：US17691014

申请日：2022-03-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Eric N. Lee ,  Jeffrey S. McNeil ,  Jonathan S. Parry ,  Lakshmi Kalpana Vakati

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

公开(公告)号：US11769561B2

公开(公告)日：2023-09-26

申请号：US17119509

申请日：2020-12-11

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  George B. Raad ,  James S. Rehmeyer ,  Jonathan S. Parry

IPC: G11C17/00 ,  G11C17/08 ,  G11C17/16 ,  G11C17/18 ,  G11C16/08 ,  G11C16/22 ,  G11C11/22 ,  G11C13/00 ,  G11C11/16

CPC classification number: G11C17/08 ,  G11C11/1653 ,  G11C11/1695 ,  G11C11/2253 ,  G11C11/2295 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0059 ,  G11C16/08 ,  G11C16/22 ,  G11C17/165 ,  G11C17/18

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.

公开(公告)号：US11768629B2

公开(公告)日：2023-09-26

申请号：US17243321

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Nadav Grosz ,  Roberto Izzi ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/08

CPC classification number: G06F3/0659 ,  G06F1/08 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673

Abstract: Methods, systems, and devices supporting techniques for memory system configuration using a queue refill time are described. A memory system may receive a command from a host system and may add the command to a command queue including a set of commands to be executed by the memory system. The memory system may determine a queue refill time of the command queue using measurements for at least one queue tag of the command queue and may adjust at least one resource of the command queue in response to the determined queue refill time. In some examples, the memory system may reallocate processing or memory resources previously allocated to the command queue, deactivate processing or memory resources previously allocated to the command queue, adjust a threshold queue depth for the command queue, or any combination thereof, among other options, based on the queue refill time.

公开(公告)号：US11714563B2

公开(公告)日：2023-08-01

申请号：US17574044

申请日：2022-01-12

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0632 ,  G06F3/0653 ,  G06F3/0673

Abstract: Methods, systems, and devices for volatile register to detect power loss are described. The memory system may receive a command to enter a first power mode having a lower power consumption than a second power mode. The memory system may store data in a register associated with the memory system before entering the first power mode (e.g., a low-power mode). The memory system may receive a command to exit the first power mode. The memory system may determine whether the data stored in the register includes one or more errors. The memory system may select a reset operation to perform to exit the first power mode based on determining whether the data stored in the register includes one or more errors.

公开(公告)号：US11687477B2

公开(公告)日：2023-06-27

申请号：US17573214

申请日：2022-01-11

Applicant: Micron Technology, Inc.

Inventor： Stephen D. Hanna ,  Jonathan S. Parry

IPC: G06F13/40 ,  G06F1/26

CPC classification number: G06F13/40 ,  G06F1/266

Abstract: Methods, systems, and devices that support signaling mechanisms for bus inversion are described. A control signal that supports transferring information from a first controller to a second controller via a bus may also be configured to indicate whether or not data that is communicated over the bus is inverted. The control signal may be a control signal that enables reception of control information at the second controller. The control signal may be controlled by the first controller when data is transmitted to the second controller and may be controlled by the second controller when data is transmitted to the first controller.

公开(公告)号：US20230197163A1

公开(公告)日：2023-06-22

申请号：US18076488

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Kishore Kumar Muchherla ,  Sead Zildzic ,  Akira Goda ,  Jonathan S. Parry ,  Violante Moschiano

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/28

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/28

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a set of commands to concurrently program a set of cells of the memory array with dummy data, the set of cells corresponding to a group of retired wordlines of the plurality of wordlines, in response to receiving the set of commands, obtaining the dummy data, and concurrently programming the set of cells with the dummy data by causing a ganged programming pulse to be applied to the set of cells.

公开(公告)号：US11599485B2

公开(公告)日：2023-03-07

申请号：US17105053

申请日：2020-11-25

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry

IPC: G06F13/16 ,  G06F1/12

Abstract: Methods, systems, and devices for status check using signaling are described. A memory system may receive ready signals from memory dies. The ready signal may indicate whether a memory die is available to receive a command. The memory system may generate an indicator of whether the memory die is available based on values of ready signals. The memory system may output the indicator to a controller over one or more pins based on generating the indicator.

公开(公告)号：US20230069603A1

公开(公告)日：2023-03-02

申请号：US17462228

申请日：2021-08-31

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Giuseppe Cariello ,  Reshmi Basu

IPC: G06F3/06

Abstract: Methods, systems, and devices for overwriting at a memory system are described. A memory system may be configured to overwrite portions of a memory array with new data, which may be associated with omitting an erase operation. For example, write operations may be performed in accordance with a first demarcation configuration to store information at a portion of a memory array. A portion of a memory system may then determine to overwrite the portion of the memory array with different or updated information, which may include performing write operations in accordance with a second demarcation configuration. The second demarcation configuration may be associated with different cell characteristics for a one or more logic states, such as different distributions of stored charge or other cell property, different demarcation characteristics, different write operations, among other differences, which may support performing an overwrite operation without first performing an erase operation.

公开(公告)号：US20230049201A1

公开(公告)日：2023-02-16

申请号：US17648396

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry ,  Chun Sum Yeung

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/20 ,  G06F11/07

Abstract: Methods, systems, and devices for techniques for retiring blocks of a memory system are described. In some examples, aspects of a memory system or memory device may be configured to determine an error for a block of memory cells. Upon determining the occurrence of the error, the memory system may identify one or more operating conditions associated with the block. For example, the memory system may determine a temperature of the block, a cycle count of the block, a quantity of times the block has experienced an error, a bit error rate of the block, and/or a quantity of available blocks in the associated system. Depending on whether a criteria associated with a respective operating condition is satisfied, the block may be enabled or retired.

公开(公告)号：US20230046535A1

公开(公告)日：2023-02-16

申请号：US17400942

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Jonathan S. Parry

IPC: G06F3/06

Abstract: Methods, systems, and devices for using a completion flag for memory operations are described. A completion flag for a memory device may indicate whether at least one access operation has been completed at the memory device. A controller may poll the completion flag, and if the completion flag indicates that at least one access operation has been completed at the memory device, the controller may poll a status register for the memory device to obtain additional information regarding one or more completed access operations at the memory device.