公开(公告)号：US10019314B2

公开(公告)日：2018-07-10

申请号：US15874895

申请日：2018-01-19

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu ,  Jian-Dong Du

IPC: G11C16/04 ,  G06F11/10 ,  G11C29/52 ,  G11C11/56 ,  G11C16/26 ,  G11C16/10

CPC classification number: G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2211/5641

Abstract: A method used for a flash memory module having a plurality of storage blocks each can be used as a first block or a second block includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks; reading out the groups of data from the first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon the randomized data to generate a second corresponding parity check code; and storing the randomized data and the second corresponding parity check code into the flash memory module as the second block.

公开(公告)号：US20170315868A1

公开(公告)日：2017-11-02

申请号：US15495997

申请日：2017-04-25

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hong-Jung Hsu

IPC: G06F11/10 ,  G11C16/04 ,  G11C11/56 ,  G11C7/10 ,  G06F12/0802 ,  G06F12/02 ,  G11C29/52 ,  G06F11/14

CPC classification number: H03M13/29 ,  G06F11/10 ,  G06F11/1072 ,  G06F11/1402 ,  G06F12/0246 ,  G06F12/0802 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C29/52 ,  G11C2211/5641 ,  H03M13/1102

Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.

公开(公告)号：US09760433B2

公开(公告)日：2017-09-12

申请号：US14666320

申请日：2015-03-24

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F11/10 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F11/1044 ,  G06F3/0679 ,  G06F11/1048 ,  G06F11/1072 ,  G06F12/02 ,  G06F12/0246 ,  G06F2003/0691 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A flash memory controlling apparatus includes a data read/write interface and a controller. The data read/write interface is arranged to couple a first flash memory and a second flash memory, wherein the first flash memory includes a first storage plane and a first buffer, and the second flash memory includes a second storage plane and a second buffer. When the read/write interface couples the first flash memory and the second flash memory, the controller is arranged to temporary store a plurality of valid data stored in the first storage plane into the second buffer. After an erase cycle is performed on the first storage plane, the controller further programs the plurality of valid data temporarily stored in the second buffer into the first storage plane.

公开(公告)号：US20170169884A1

公开(公告)日：2017-06-15

申请号：US15431643

申请日：2017-02-13

Applicant: Silicon Motion Inc.

Inventor： Ching-Hui Lin ,  Tsung-Chieh Yang

IPC: G11C11/56

CPC classification number: G11C11/5635 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10

Abstract: A control device for writing data into a flash memory unit includes a determining circuit and a writing circuit. The determining circuit is arranged to determine a data polarity of an n-th data bit of the flash memory unit when writing data into the flash memory unit for the n-th time. The writing circuit is arranged to inject an n-th electrical charge amount to a floating gate of the flash memory unit according to the data polarity of the n-th data bit only. The determining circuit is further arranged to determine the data polarity of an (n+1)-th data bit of the flash memory unit when writing data into the flash memory unit for the (n+1)-th time. The writing circuit is further arranged to selectively inject an (n+1)-th electrical charge amount to the floating gate of the flash memory unit according to the data polarity of the (n+1)-th data bit only.

公开(公告)号：US20170075755A1

公开(公告)日：2017-03-16

申请号：US15260330

申请日：2016-09-09

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Sheng-I Hsu

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/02 ,  H03M13/09 ,  H03M13/29

CPC classification number: H03M13/2906 ,  G06F11/1012 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/403 ,  G06F2212/7201 ,  H03M13/09 ,  H03M13/13

Abstract: A data storage system includes: a processing circuit arranged to receive a data bytes from a host; a calculating circuit arranged to generate a cyclic redundancy check code according to a logical block address, and combine the cyclic redundancy check code and the data bytes to be a data sector; and an encoding circuit arranged to encode the data sector to generate an error checking and correcting code, and combine the data sector and the error checking and correcting code to be a storing data.

Abstract translation: 数据存储系统包括：处理电路，被布置成从主机接收数据字节; 计算电路，被配置为根据逻辑块地址生成循环冗余校验码，并将所述循环冗余校验码与所述数据字节组合为数据扇区; 以及编码电路，被配置为对数据扇区进行编码以产生错误校验和校正码，并将数据扇区和错误校验和校正码组合成存储数据。

公开(公告)号：US09588709B2

公开(公告)日：2017-03-07

申请号：US14983566

申请日：2015-12-30

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G11C16/04 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract translation: 一种用于控制闪速存储器模块的闪存控制器包括用于接收第一数据和第二数据的通信接口; 以及处理电路，用于根据闪速存储器模块中存储的数据量来动态地控制闪存模块的数据写入模式。 如果在通信接口接收到第一数据时闪存模块中存储的数据量小于第一阈值，则处理电路控制闪存模块，使得第一数据被写入第一数据块， 每单元位数模式。 如果在通信接口接收到第二数据时闪存模块中存储的数据量大于第一阈值，则处理电路控制闪存模块，使得第二数据被写入第二数据块， 每单元位数模式。

公开(公告)号：US09520184B2

公开(公告)日：2016-12-13

申请号：US14615435

申请日：2015-02-06

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C11/56 ,  G11C7/02 ,  G11C16/04 ,  G11C16/10 ,  G11C7/10

CPC classification number: G11C11/5628 ,  G11C7/02 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10

Abstract: The present invention provides a method for writing a data into a flash memory, wherein the flash memory is a Triple-Level Cell flash memory, and each storage unit of the flash memory is implemented by a floating-gate transistor and each storage unit supports eight write voltage levels, and the method includes: adjusting the data bit by bit to generate a pseudo-random bit sequence; and writing the pseudo-random bit sequence into the flash memory with only two specific voltage levels of the eight write voltage levels.

Abstract translation: 本发明提供一种将数据写入闪速存储器的方法，其中闪速存储器是三电平单元闪速存储器，并且闪存的每个存储单元由浮栅晶体管实现，并且每个存储单元支持八 写入电压电平，并且该方法包括：逐位地调整数据以生成伪随机位序列; 以及只将八个写入电压电平的两个特定电压电平写入闪速存储器中的伪随机位序列。

公开(公告)号：US20160329095A1

公开(公告)日：2016-11-10

申请号：US15213419

申请日：2016-07-19

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Hsiao-Te Chang ,  Wen-Long Wang

IPC: G11C11/56 ,  G11C16/08

CPC classification number: G11C11/5642 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0679 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/26

Abstract: A memory access module for performing memory access management of a storage device including a plurality of storage cells includes: sensing means for performing a plurality of sensing operations respectively corresponding to a plurality of different sensing voltages in order to generate at least a first digital value of a storage cell, wherein each subsequent sensing operation corresponds to a sensing voltage which is determined according to a result of the previous sensing operation; processing means for using the first digital value to obtain soft information of a bit stored in the storage cell; and decoding means for using the soft information to perform soft decoding.

Abstract translation: 一种用于执行包括多个存储单元的存储设备的存储器访问管理的存储器访问模块包括：感测装置，用于执行分别对应于多个不同感测电压的多个感测操作，以便产生至少第一数字值 存储单元，其中每个后续感测操作对应于根据先前感测操作的结果确定的感测电压; 处理装置，用于使用第一数字值来获得存储在存储单元中的位的软信息; 以及用于使用软信息进行软解码的解码装置。

公开(公告)号：US09437328B2

公开(公告)日：2016-09-06

申请号：US14089730

申请日：2013-11-25

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C29/56 ,  G11C29/14 ,  G06F11/10

CPC classification number: G11C29/56012 ,  G06F11/1048 ,  G11C29/14 ,  G11C29/56004 ,  G11C2029/5602

Abstract: A device under test has a connection interface, a controller, and a functional block. The connection interface is used to receive a test pattern transmitted at a first clock rate and output a functional test result. The controller is used to sample the test pattern by using a second clock rate and accordingly generate a sampled test pattern, wherein the second clock rate is higher than the first clock rate. The functional block is used to perform a designated function upon the sampled test pattern and accordingly generate the functional test result.

Abstract translation: 被测设备具有连接接口，控制器和功能块。 连接接口用于接收以第一时钟速率发送的测试码，并输出功能测试结果。 控制器用于通过使用第二时钟速率对测试模式进行采样，并因此产生采样的测试模式，其中第二时钟速率高于第一时钟速率。 功能块用于在采样的测试图案上执行指定的功能，从而产生功能测试结果。

公开(公告)号：US09417958B2

公开(公告)日：2016-08-16

申请号：US13911096

申请日：2013-06-06

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C11/34 ,  G11C16/06 ,  G06F11/10 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C29/52 ,  G11C16/04

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2211/5641

Abstract: A memory control method is used for controlling a flash memory. The flash memory includes a first memory element and a second memory element. The second memory element includes multiple blocks and each block includes multiple pages. In this method, original data are written to the first memory element. Input data are obtained by reading the original data from the first memory element. The input data includes multiple input data rows. The input data rows are divided into data groups. Each input data row corresponding to each data row is written to a corresponding data page on the second memory element. A parity row corresponding to each data group is written to a data page on the second memory element. The number of data rows for each data group is smaller than the number of each block in the second memory element.