公开(公告)号：US20020063268A1

公开(公告)日：2002-05-30

申请号：US10056564

申请日：2001-10-26

Applicant: STMicroelectronics S.r.I.

Inventor： Bruno Vajana ,  Matteo Patelmo

IPC: H01L021/82 ,  H01L027/10

CPC classification number: H01L27/11226 ,  H01L23/573 ,  H01L27/02 ,  H01L27/112 ,  Y10S257/922

Abstract: A read only memory (ROM) device includes a semiconductor substrate having a first type of conductivity, and a plurality of memory cells on the semiconductor substrate. Each memory cell includes first and second regions of a second conductivity type opposite the first conductivity type. A first dielectric layer is on the plurality of memory cells, and a plurality of first contacts extend through the first dielectric layer for contacting the first regions. A second dielectric layer is on the first dielectric layer and the plurality of first contacts. A plurality of second contacts extend through the second dielectric layer and overlie the corresponding second regions. The plurality of second contacts define interconnection contacts by further extending through the first dielectric layer for contacting the second regions for memory cells programmed in a conductive state, and false interconnection contacts by not extending through the first dielectric layer for contacting the second regions for memory cells programmed in a non-conductive state.

Abstract translation: 只读存储器（ROM）器件包括具有第一类型导电性的半导体衬底和半导体衬底上的多个存储单元。 每个存储单元包括与第一导电类型相反的第二导电类型的第一和第二区域。 第一介电层位于多个存储单元上，并且多个第一触点延伸穿过第一介电层以接触第一区域。 第二电介质层位于第一电介质层和多个第一接触件上。 多个第二触点延伸穿过第二介电层并且覆盖相应的第二区域。 多个第二触点通过进一步延伸穿过第一介电层来限定互连触点，以接触用于以导电状态编程的存储器单元的第二区域，以及通过不延伸穿过第一介电层以接触存储器单元的第二区域的假互连触点 编程在非导通状态。

公开(公告)号：US20020048187A1

公开(公告)日：2002-04-25

申请号：US09972726

申请日：2001-10-04

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Pierin ,  Stefano Gregori ,  Rino Micheloni ,  Osama Khouri ,  Guido Torelli

IPC: G11C011/34

CPC classification number: G11C16/30 ,  G11C5/145 ,  G11C7/06 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/26

Abstract: A multilevel nonvolatile memory includes a supply line supplying a supply voltage, a voltage boosting circuit supplying a boosted voltage, higher than the supply voltage, a boosted line connected to the voltage boosting circuit and a reading circuit including at least one comparator. The comparator includes a first and a second input, a first and a second output, at least one amplification stage connected to the boosted line, and a boosted line latch stage connected to the supply line.

Abstract translation: 多级非易失性存储器包括提供电源电压的电源线，提供高于电源电压的升压电压的升压电路，连接到升压电路的升压线路和包括至少一个比较器的读取电路。 比较器包括第一和第二输入，第一和第二输出，连接到升压线路的至少一个放大级和连接到电源线的升压线路锁存级。

公开(公告)号：US20020040995A1

公开(公告)日：2002-04-11

申请号：US09960254

申请日：2001-09-20

Applicant: STMicroelectronics S.r.I.

Inventor： Nicola Zatelli ,  Massimo Atti ,  Elisabetta Palumbo ,  Cosimo Torelli

IPC: H01L029/76 ,  H01L029/94

CPC classification number: H01L29/41725 ,  H01L29/7835

Abstract: A lateral DMOS transistor having a drain region which comprises a high-concentration portion with which the drain electrode is in contact and a low-concentration portion which is delimited by the channel region. In addition to the conventional source, drain, body and gate electrodes, the transistor has an additional electrode in contact with a point of the low-concentration portion of the drain region which is close to the channel. The additional electrode permits a direct measurement of the electric field in the gate dielectric and thus provides information which can be used both for characterizing the transistor and selecting its dimensions and for activating devices for protecting the transistor and/or other components of an integrated circuit containing the transistor.

Abstract translation: 一种具有漏极区域的横向DMOS晶体管，其包括漏电极接触的高浓度部分和由沟道区域限定的低浓度部分。 除了常规的源极，漏极，体和栅电极之外，晶体管还具有与漏极区域的靠近沟道的低浓度部分的点接触的附加电极。 附加电极允许直接测量栅极电介质中的电场，并且因此提供可以用于表征晶体管并选择其尺寸的信息，并且用于激活用于保护晶体管和/或其中包含的集成电路的其它部件的器件 晶体管。

公开(公告)号：US20020021596A1

公开(公告)日：2002-02-21

申请号：US09881581

申请日：2001-06-14

Applicant: STMicroelectronics S.r.I.

Inventor： Paolo Rolandi

IPC: G11C029/00

CPC classification number: G11C16/102 ,  G11C7/16 ,  G11C16/18

Abstract: An integrated circuit for storing data, and for application in a memory card that operates in cooperation with at least one of an external acquisition system and an external processing system includes input/output terminals for receiving the data to be stored, and an electrically programmable non-volatile memory for storing the data in digital format. The memory includes a first terminal for receiving a programming signal for enabling storage of the data, and a second terminal for receiving a reading signal for enabling output of the stored data via the input/output terminals. A memory control circuit is connected to the first and second terminals of the electrically programmable non-volatile memory, and to the input/output terminals for generating programming and reading signals based upon the command signal. The electrically programmable non-volatile memory is erasable by electromagnetic radiation for permitting a non-electrical erasure of the stored data.

Abstract translation: 一种用于存储数据并用于应用于与外部采集系统和外部处理系统中的至少一个协同操作的存储卡的集成电路，包括用于接收要存储的数据的输入/输出端子， 用于以数字格式存储数据的非易失性存储器。 存储器包括用于接收用于使数据存储的编程信号的第一端子，以及用于接收经由输入/输出端子输出存储的数据的读取信号的第二端子。 存储器控制电路连接到电可编程非易失性存储器的第一和第二端子以及输入/输出端子，用于基于该命令信号产生编程和读取信号。 电可编程非易失性存储器可通过电磁辐射进行擦除，以允许存储数据的非电擦除。

公开(公告)号：US20010034819A1

公开(公告)日：2001-10-25

申请号：US09774542

申请日：2001-01-31

Applicant: STMicroelectronics S.r.I.

Inventor： Salvatore Nicosia ,  Francesco Tomaiuolo ,  Fabrizio Campanale ,  Luca Giuseppe De Ambroggi ,  Promod Kumar

IPC: G06F012/00

CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

Abstract: An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.

Abstract translation: 具有交错数据路径的交错存储器包括被分成第一存储单元组和第二存储单元组的存储器单元的阵列，分别耦合到第一和第二存储单元组的读出放大器的第一和第二阵列，以及 分别耦合到第一和第二读出放大器阵列的第一和第二读取寄存器。 控制和定时电路连接到第一和第二读出放大器阵列，并且具有用于接收外部产生的命令信号的输入，以及用于提供路径选择信号和控制信号的输出。 第三寄存器连接到第一和第二读取寄存器，并且具有用于根据路径选择信号接收其中的读取数据的输入。 一个通道阵列连接到第三寄存器，并被控制信号共同控制，以便将存储在第三寄存器中的读取数据传送到输出缓冲器阵列。

公开(公告)号：US20010026194A1

公开(公告)日：2001-10-04

申请号：US09778677

申请日：2001-02-07

Applicant: STMicroelectronics S.r.I.

Inventor： Luciano Tomasini ,  Giancarlo Clerici

IPC: H03F003/18

CPC classification number: H03F3/3001

Abstract: An operational amplifier includes a first stage, and a second stage with an input connected to an output of the first stage and an output connected to a load. The second stage includes between its input and its output a first signal path for driving the load in a first direction, and a second signal path for driving the load in the opposite direction. The first and second signal paths have substantially equal gains for small signals, substantially equal output impedances for small and large signals, and substantially equal output-current capabilities.

Abstract translation: 运算放大器包括第一级和第二级，其输入端连接到第一级的输出端，输出端连接到负载。 第二级在其输入和输出之间包括用于沿第一方向驱动负载的第一信号路径和用于沿相反方向驱动负载的第二信号路径。 第一和第二信号路径对于小信号具有基本上相等的增益，对于小信号和大信号基本相等的输出阻抗以及基本相等的输出电流能力。

公开(公告)号：US12205651B2

公开(公告)日：2025-01-21

申请号：US17940753

申请日：2022-09-08

Applicant: STMicroelectronics S.r.I.

Inventor： Gianbattista Lo Giudice ,  Antonino Conte

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/26

Abstract: A method for accessing memory cells in an array of memory cells storing respective data signals, wherein memory cells in the array of memory cells have a first, resp. second, node selectively couplable to respective bitline branches in a first, resp. second, set of bitline branches, wherein the first and the second set of bitline branches provide at least one bitline capacitance configured to store a bias level of charge in response to being charged.

公开(公告)号：US11922979B2

公开(公告)日：2024-03-05

申请号：US18146034

申请日：2022-12-23

Applicant: STMicroelectronics S.r.I.

Inventor： Marco Mazzini ,  Marco Ciuffolini ,  Enrico Mammei ,  Paolo Pulici

IPC: G11B5/02 ,  G05F1/56 ,  G11B5/012 ,  H05B3/22 ,  G11B5/00

CPC classification number: G11B5/012 ,  G05F1/56 ,  H05B3/22 ,  G11B2005/0021

Abstract: In accordance with an embodiment, a circuit is configured to vary an intensity of a drive current of a resistive heater element based on the digital control signal. The circuit includes and output circuit configured to control a respective slew rate and an electric energy dissipated in the resistive heater element independently of a resistance value of the resistive heater element.

公开(公告)号：US20240048131A1

公开(公告)日：2024-02-08

申请号：US18350380

申请日：2023-07-11

Applicant: STMicroelectronics S.r.I.

Inventor： Marco Borghese

IPC: H03K3/03 ,  H02M3/157 ,  H03K7/08 ,  H02M1/00

CPC classification number: H03K3/0315 ,  H02M3/157 ,  H03K7/08 ,  H02M1/0025

Abstract: A control circuit for a switching stage of an electronic converter includes a PWM signal generator that generates a PWM signal to drive the switching stage of the electronic converter. A loop comparator circuit receives the regulated output voltage of the electronic converter and receives a sum signal from an adder circuit. The loop comparator circuit generates a comparison signal having a first or second logic value in response to the regulated output voltage reaching the sum signal or failing to reach the sum signal. The adder circuit generates the sum signal as a sum of a reference voltage and a programmable offset voltage that is generated by a programmable voltage generator based on a digital word signal. A feedback circuit is coupled to the loop comparator circuit and the PWM signal generator, and provides the digital word signal to the programmable voltage generator.

公开(公告)号：US20230384459A1

公开(公告)日：2023-11-30

申请号：US18312157

申请日：2023-05-04

Applicant: STMicroelectronics S.r.I.

Inventor： Gaetano Rivela

IPC: G01S19/24 ,  G01S19/04

CPC classification number: G01S19/243 ,  G01S19/04

Abstract: In accordance with an embodiment, a system includes a phase-locked loop (PLL) configured to provide a first local oscillator (LO) signal and a voltage-controlled oscillator (VCO) signal; a first quadrature demodulator configured to downconvert global navigation satellite system signals to produce a first intermediate frequency (IF) signal; a first signal processing chain configured to pass the first IF signal; a second signal processing chain comprising a first frequency divider configured to produce a second LO signal based on the first LO signal, and a second quadrature demodulator configured to convert the first IF signal to a second IF signal using the second LO signal; and a third signal processing chain comprising a second frequency divider configured to produce a third LO signal based on the VCO signal, and a third quadrature demodulator configured to convert the first IF signal to a third IF signal using the third LO signal.