公开(公告)号：US09793156B1

公开(公告)日：2017-10-17

申请号：US15262231

申请日：2016-09-12

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang

IPC: H01L23/528 ,  H01L21/283 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/7681 ,  H01L21/76849 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228

Abstract: Methods are provided for fabricating self-aligned, low resistance metal interconnect structures, as well as semiconductor devices comprising such metal interconnect structures. A first metal line is formed in a first insulating layer. An etch stop layer is formed by selectively depositing dielectric material on the first insulating layer. A second insulating layer is formed over the etch stop layer and the first metal line, and an opening is etched in the second insulating layer selective to the etch stop layer to prevent etching of the first insulating layer. The opening is filled with a metallic material to form a second metal line in contact with the first metal line. The first and second metal lines are formed with aspect ratios that are less than 2.5 to minimize resistivity of the metal lines. The first and second metal lines collectively form a single metal line of an interconnect structure.

公开(公告)号：US09786605B1

公开(公告)日：2017-10-10

申请号：US15167500

申请日：2016-05-27

Applicant: International Business Machines Corporation

Inventor： Daniel C Edelstein ,  Chih-Chao Yang

IPC: H01L21/60 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/53238 ,  H01L21/486 ,  H01L21/76856 ,  H01L21/76871 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657

Abstract: In one aspect of the invention, a method to create an advanced through silicon via structure is described. A high aspect ratio through substrate via in a substrate is provided. The through substrate via has vertical sidewalls and a horizontal bottom. A metallic barrier layer is deposited on the sidewalls of the through substrate via. A nitridation process is performed to convert a surface portion of the metallic barrier layer to a nitride surface layer. The nitride surface layer enhances the nucleation of subsequent depositions. A metal is deposited to fill the through substrate via. Another aspect of the invention is a device created by the method.

公开(公告)号：US09786596B2

公开(公告)日：2017-10-10

申请号：US15065297

申请日：2016-03-09

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Alexander Reznicek ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L23/525 ,  H01L29/20 ,  H01L21/308 ,  H01L21/3213

CPC classification number: H01L23/5256 ,  H01L29/20

Abstract: A fuse structure is provided above a first portion of a semiconductor material. The fuse structure includes a first end region containing a first portion of a metal structure having a first thickness, a second end region containing a second portion of the metal structure having the first thickness, and a neck region located between the first and second end regions. The neck region contains a third portion of the metal structure having a second thickness that is less than the first thickness, wherein a portion of the neck region is located in a gap positioned between a bottom III-V compound semiconductor material portion and a top III-V compound semiconductor material portion.

公开(公告)号：US20170278800A1

公开(公告)日：2017-09-28

申请号：US15082902

申请日：2016-03-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Praneet Adusumilli ,  Alexander Reznicek ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/53266 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/485

Abstract: A low resistance middle-of-line interconnect structure is formed without liner layers. A contact metal layer is deposited on source/drain regions of field-effect transistors and directly on the surfaces of trenches within a dielectric layer using plasma enhancement. Contact metal fill is subsequently provided by thermal chemical vapor deposition. The use of low-resistivity metal contact materials such as ruthenium is facilitated by the process. The process further facilitates the formation of metal silicide regions on the source/drain regions.

公开(公告)号：US20170278790A1

公开(公告)日：2017-09-28

申请号：US15083216

申请日：2016-03-28

Applicant: International Business Machines Corporation

Inventor： Daniel C. Edelstein ,  Chih-Chao Yang

IPC: H01L23/525 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5256 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238

Abstract: In one aspect of the invention, a method for fabricating an e-Fuse device is described. A trench structure is provided. The trench structure includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions. The trench is provided in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The trench is filled with copper. An annealing step converts the copper to create a large grained copper structure in the anode and cathode regions and a fine grained copper structure in the fuse element. Another aspect of the invention is an e-Fuse device which includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper structure and the fuse element is comprised of a fine grained copper structure.

公开(公告)号：US09768118B1

公开(公告)日：2017-09-19

申请号：US15269247

申请日：2016-09-19

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/764

CPC classification number: H01L23/5283 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor device includes a semiconductor substrate, and a dielectric layer on an upper surface of the semiconductor substrate. A contact stack is formed in the dielectric layer. The contact stack includes an electrically conductive contact element, and a contact liner on first and second opposing sidewalls of the contact element. A first air gap is interposed between the dielectric layer and the contact liner on the first side wall, and a second air gap interposed between the dielectric layer and the contact liner on the second side wall.

公开(公告)号：US20170263547A1

公开(公告)日：2017-09-14

申请号：US15065226

申请日：2016-03-09

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Alexander Reznicek ,  Oscar van der Straten ,  Chih-Chao Yang

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53261 ,  H01L23/53266

Abstract: A semiconductor structure is provided that includes a first interconnect dielectric layer containing a first interconnect metal structure embedded therein. A second interconnect dielectric layer containing a second interconnect metal structure embedded therein is located atop the first interconnect dielectric layer. A metallic blocking layer is present that separates a surface of the second interconnect metal structure from a surface of the first interconnect metal structure. The metallic blocking layer has a lower resistivity than the first and second interconnect metal structures. The metallic blocking layer prevents electromigration of metallic ions from the first and second interconnect metal structure.

公开(公告)号：US09741577B2

公开(公告)日：2017-08-22

申请号：US14956720

申请日：2015-12-02

Applicant: International Business Machines Corporation

Inventor： Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L29/51 ,  H01L21/285 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L21/823871 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76882 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/495 ,  H01L29/51

Abstract: A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.

公开(公告)号：US09735051B2

公开(公告)日：2017-08-15

申请号：US14967618

申请日：2015-12-14

Applicant: International Business Machines Corporation

Inventor： Conal E. Murray ,  Chih-Chao Yang

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76807 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53266

Abstract: Methods are devices are provided in which interconnection structures are formed using metal reflow techniques. For example, a method to fabricate a semiconductor device includes forming an opening in an ILD (inter-level dielectric) layer. The opening includes a via hole and a trench. A layer of diffusion barrier material is deposited to cover the ILD layer and to line the opening with the diffusion barrier material. A layer of first metallic material is deposited on the layer of diffusion barrier material to cover the ILD layer and to line the opening with the first metallic material. A reflow process is performed to allow the layer of first metallic material to reflow into the opening and at least partially fill the via hole with the first metallic material. A layer of second metallic material is deposited to at least partially fill a remaining portion of the opening in the ILD layer.

公开(公告)号：US09728399B1

公开(公告)日：2017-08-08

申请号：US15217504

申请日：2016-07-22

Applicant: International Business Machines Corporation

Inventor： Daniel C Edelstein ,  Chih-Chao Yang

IPC: H01L21/02 ,  H01L23/528 ,  H01L21/768 ,  H01L21/321 ,  H01L23/532 ,  H01L23/52 ,  H01L21/28

CPC classification number: H01L23/53223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02329 ,  H01L21/28 ,  H01L21/3212 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/532 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53266

Abstract: In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern has parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A first metal layer is deposited on the element enriched surface layer. A first thermal anneal is performed which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating a liner which is an alloy of the first metal and selected element. A second metal layer is deposited. A second thermal anneal is performed which reflows the second metal layer to fill a remaining portion of the conductive line trenches. Another aspect of the invention is a device formed by the process.