公开(公告)号：US09450000B2

公开(公告)日：2016-09-20

申请号：US14462724

申请日：2014-08-19

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Michel Marty ,  Sebastien Jouan ,  Laurent Frey ,  Salim Boutami

IPC: H01L31/062 ,  H01L27/144 ,  H01L31/0232 ,  H01L27/146 ,  H01L31/107 ,  H01L29/16 ,  H01L29/49 ,  H01L29/66 ,  H01L31/101 ,  H01L31/18

CPC classification number: H01L27/1443 ,  H01L27/14625 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/6656 ,  H01L31/02327 ,  H01L31/1016 ,  H01L31/107 ,  H01L31/1804

Abstract: A photodiode includes at least one central pad arranged on a light-receiving surface of a photodiode semiconductor substrate. The pad is made of a first material and includes lateral sidewalls surrounded by a spacer made of a second material having a different optical index than the first material. The lateral dimensions of the pad are smaller than an operating wavelength of the photodiode. Both the first and second materials are transparent to that operating wavelength. The pads and spacers are formed at a same time gate electrodes and sidewall spacers of MOS transistors are formed.

Abstract translation: 光电二极管包括布置在光电二极管半导体衬底的光接收表面上的至少一个中心衬垫。 衬垫由第一材料制成，并且包括由具有与第一材料不同的光学折射率的第二材料制成的间隔件包围的侧壁。 焊盘的横向尺寸小于光电二极管的工作波长。 第一和第二材料都对该工作波长是透明的。 焊盘和间隔物同时形成栅电极和MOS晶体管的侧壁间隔物。

公开(公告)号：US09444371B2

公开(公告)日：2016-09-13

申请号：US14378267

申请日：2013-02-13

Applicant: Commissariat a l'energie atomique et aux ene alt ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Emmanuel Ollier ,  Stephane Monfray ,  Thomas Skotnicki ,  Ulrich Soupremanien

IPC: H02N2/18 ,  H01L41/047 ,  H01L41/08

CPC classification number: H02N2/185 ,  H01L41/047 ,  H01L41/08 ,  H02N2/18

Abstract: A device for converting heat energy into electrical energy including cells, the cells including: a first cavity with one wall for contacting a heat source; a second cavity with one wall for contacting a cold source; a primary channel between the first cavity and the second cavity transporting a fluid as liquid drops, the primary channel providing transport of liquid fluid drops from the second cavity to the first cavity; at least one secondary channel between the first cavity and the second cavity transporting the fluid as a gas; a piezoelectric material provided in one of the cavities; and a fluid as a liquid and gas contained within the cell.

Abstract translation: 一种用于将热能转换成包括电池的电能的装置，所述电池包括：具有用于接触热源的一个壁的第一腔; 具有用于接触冷源的一个壁的第二腔; 所述第一腔和所述第二腔之间的主要通道以液体的形式输送流体，所述主要通道提供液体流体液体从所述第二腔向所述第一腔的输送; 所述第一腔和所述第二腔之间的至少一个次通道作为气体输送所述流体; 设置在其中一个空腔中的压电材料; 以及作为包含在电池内的液体和气体的流体。

公开(公告)号：US20160233258A1

公开(公告)日：2016-08-11

申请号：US14923799

申请日：2015-10-27

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Axel CROCHERIE ,  Jean-Pierre ODDOU ,  Stéphane ALLEGRET-MARET ,  Hugues LEININGER

IPC: H01L27/146

CPC classification number: H01L27/14621 ,  H01L27/14607 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685

Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.

Abstract translation: 包括像素阵列的彩色图像传感器形成在具有接收照明的背面的半导体层中。 绝缘导电壁从背面渗入半导体层并将像素彼此分开。 对于每个像素，彩色像素从背面渗入半导体层的厚度的5至30％，并且占据由壁限定的表面积的至少90％。 导电层从过滤器的侧壁一直延伸到壁。

公开(公告)号：US20160181382A1

公开(公告)日：2016-06-23

申请号：US14577656

申请日：2014-12-19

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  David Barge

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L29/41783 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

Abstract: A method for forming a transistor includes defining agate structure on a top surface of a first semiconductor layer of a silicon-on-insulator (SOI) substrate. The gate structure includes an insulating cover. A second semiconductor layer is then conformally deposited. The deposited second semiconductor layer includes an epitaxial portion on surfaces of the first semiconductor layer and an amorphous portion on surfaces of the insulating cover. The amorphous portion is then removed using a selective etch. The remaining epitaxial portion forms faceted raised source-drain structures on either side of the transistor gate structure. A slope of the sloped surface for the facet is dependent on the process parameters used during the conformal deposition.

Abstract translation: 一种用于形成晶体管的方法包括在绝缘体上硅（SOI）衬底的第一半导体层的顶表面上限定玛瑙结构。 门结构包括绝缘盖。 然后共形沉积第二半导体层。 沉积的第二半导体层包括在第一半导体层的表面上的外延部分和绝缘盖表面上的非晶部分。 然后使用选择性蚀刻除去非晶部分。 剩余的外延部分在晶体管栅极结构的任一侧上形成刻面凸起的源极 - 漏极结构。 用于小平面的倾斜表面的斜率取决于在保形沉积期间使用的工艺参数。

公开(公告)号：US09356094B2

公开(公告)日：2016-05-31

申请号：US13907547

申请日：2013-05-31

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Aomar Halimaoui ,  Daniel Bensahel

IPC: H01L21/20 ,  H01L29/02 ,  H01L29/06 ,  H01L21/762 ,  H01L21/764 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/76262 ,  H01L21/764

Abstract: A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.

公开(公告)号：US20160118953A1

公开(公告)日：2016-04-28

申请号：US14981189

申请日：2015-12-28

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Frederic Gianesello ,  Romain Pilard ,  Cedric Durand

IPC: H03H7/42 ,  H04W88/02 ,  H01F27/40 ,  H01F27/28 ,  H01F27/29

CPC classification number: H03H7/42 ,  H01F27/2804 ,  H01F27/29 ,  H01F27/38 ,  H01F27/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H04W88/02 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.

公开(公告)号：US20160109732A1

公开(公告)日：2016-04-21

申请号：US14981139

申请日：2015-12-28

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Robert Manouvrier ,  Frederic Boeuf

IPC: G02F1/025

CPC classification number: G02F1/025 ,  G02F1/225 ,  G02F2001/212

Abstract: An electro-optical phase shifter to be located in an optical waveguide may include a rib of a semiconductor material extending along a length of the optical waveguide and a control structure configured to modify a concentration of carriers in the rib according to a control voltage present between first and second control terminals of the phase shifter. The control structure may include a conductive layer covering a portion of the rib and electrically connected to a first of the control terminals. An insulating layer may be configured to electrically isolate the conductive layer from the rib.

Abstract translation: 位于光波导中的电光移相器可以包括沿着光波导的长度延伸的半导体材料的肋，以及控制结构，其被配置为根据存在于所述肋之间的控制电压来修改肋中的载流子的浓度 移相器的第一和第二控制端子。 控制结构可以包括覆盖肋的一部分并电连接到第一控制端的导电层。 绝缘层可以被配置为将导电层与肋电隔离。

公开(公告)号：US20160104730A1

公开(公告)日：2016-04-14

申请号：US14973344

申请日：2015-12-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nayera Ahmed ,  François Roy

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14643 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/14698

Abstract: A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer.

公开(公告)号：US20160079388A1

公开(公告)日：2016-03-17

申请号：US14855834

申请日：2015-09-16

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Christian ARVET ,  Sébastien BARNOLA ,  Sébastien LAGRASTA ,  Nicolas POSSEME

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/283 ,  H01L21/311

CPC classification number: H01L29/6656 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66628

Abstract: The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of semiconductor material surrounding the gate, including forming a superficial layer covering the gate and the peripheral region; partially removing the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks; and selective etching of the dielectric layer vis-à-vis the material of the residual part of the superficial layer and vis-à-vis the semiconductor material.

Abstract translation: 在晶体管栅极的侧面制造间隔物，包括形成覆盖栅极的介电层和围绕栅极的半导体材料层的外围区域的步骤，包括形成覆盖栅极和外围区域的表面层; 部分去除表层，构造成在外围区域完全除去表层，同时在侧面保留表层的残留部分; 并且相对于表层的残余部分的材料和相对于半导体材料的材料的电介质层的选择性蚀刻。

公开(公告)号：US09240325B2

公开(公告)日：2016-01-19

申请号：US14498091

申请日：2014-09-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Sébastien Barnola ,  Yves Morand ,  Heimanu Niebojewski

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/283 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/42372 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

Abstract translation: 一种方法包括在有源区的表面上形成栅极堆叠，包括沉积第一介电层; 沉积栅极导电层; 沉积第一金属层; 沉积第二金属层; 沉积第二电介质层; 部分地蚀刻栅极堆叠以在有源区上形成栅极区; 在活动区域​​上的栅极区域的任一侧上制造绝缘垫片; 制造源极和漏极区域; 在源极和漏极区域的表面上形成硅化物区域; 在活性区域的栅极区域中蚀刻在第一金属层上停止的第二介电层和第二金属层，以在绝缘间隔物之间​​形成空腔; 在活动区域​​上的栅极区域的第一金属层的表面上形成保护塞，其中保护塞填充空腔。