公开(公告)号：US11876095B2

公开(公告)日：2024-01-16

申请号：US17367447

申请日：2021-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L27/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/311 ,  H01L27/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L27/0886 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66818 ,  H01L21/845

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

公开(公告)号：US20240016063A1

公开(公告)日：2024-01-11

申请号：US17884528

申请日：2022-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu ,  Shun-Yu Huang ,  Yi-Wei Tseng

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: An MRAM structure includes an MTJ, a first SOT element, a conductive layer and a second SOT element disposed from bottom to top. A protective layer is disposed on the second SOT element. The protective layer covers and contacts a top surface of the second SOT element. The protective layer is an insulator. A conductive via penetrates the protective layer and contacts the second SOT element.

公开(公告)号：US20240016062A1

公开(公告)日：2024-01-11

申请号：US17874327

申请日：2022-07-27

Applicant: United Microelectronics Corp.

Inventor： Shun-Yu Huang ,  Yi-Wei Tseng ,  Chih-Wei Kuo ,  Yi-Xiang Chen ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/02

Abstract: A method of fabricating an MTJ device is provided including the following process. A first via is formed in the first dielectric layer. A first electrode layer is formed on the first dielectric layer and the first via. An MTJ stack layer is formed on the first electrode layer. A patterned second electrode layer is formed on the MTJ stack layer and used as a mask. A first ion beam etching process is performed to etch the patterned second electrode layer and pattern the MTJ stack layer and the first electrode layer to form a second electrode, an MTJ stack structure, and a first electrode. A first protective layer is formed to cover the second electrode and the MTJ stack structure. A second ion beam etching process is performed to remove a portion of the MTJ stack structure and a portion of the first electrode.

公开(公告)号：US20240014323A1

公开(公告)日：2024-01-11

申请号：US17903072

申请日：2022-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Wei PAN ,  Sheng CHO

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/06 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L27/0688 ,  H01L29/0847 ,  H01L21/823431 ,  H01L21/823418

Abstract: A semiconductor device includes a substrate; a fin structure disposed over the substrate; a gate structure disposed over the substrate, wherein an extension direction of the fin structure intersects an extension direction of the gate structure; and a first well disposed under the gate structure, corresponding to an emitter region of the semiconductor device, and having a first conductivity type, wherein the first well is adjacent to a well block layer, and the well block layer is disposed under the gate structure in the emitter region; wherein the well block layer has a first doping concentration of a well implant, the first well has a second doping concentration of the well implant, and the first doping concentration is less than the second doping concentration.

公开(公告)号：US20240014307A1

公开(公告)日：2024-01-11

申请号：US17888523

申请日：2022-08-16

Applicant: United Microelectronics Corp.

Inventor： Wei Jen Chen ,  Kai Lin Lee

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/7786 ,  H01L29/66462 ,  H01L29/42316 ,  H01L29/401

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the HEMT device are provided. The HEMT device includes a substrate, a channel layer, a barrier layer, and a gate structure. The substrate has at least one active region. The channel layer is disposed on the at least one active region. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The gate structure includes a metal layer and a P-type group III-V semiconductor layer vertically disposed between the metal layer and the barrier layer. The P-type group III-V semiconductor layer includes a lower portion and an upper portion on the lower portion, and the upper portion has a top area greater than a top area of the lower portion.

公开(公告)号：US20240014082A1

公开(公告)日：2024-01-11

申请号：US17891090

申请日：2022-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Feng Hsu

IPC: H01L23/13 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/13 ,  H01L23/3672 ,  H01L23/3733 ,  H01L21/4871

Abstract: The invention provides a semiconductor structure, which comprises a chip comprising a substrate, wherein the substrate has a front surface and a back surface, and the front surface of the substrate comprises a circuit layer, the back surface of the substrate comprises a plurality of microstructures, and a thermal interface material located on the back surface of the substrate, and the thermal interface material contacts the microstructures directly.

公开(公告)号：US11871585B2

公开(公告)日：2024-01-09

申请号：US17389310

申请日：2021-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wei Wang ,  Yi-An Shih ,  Huan-Chi Ma

IPC: H10B61/00 ,  H10N50/85

CPC classification number: H10B61/00 ,  H10N50/85

Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.

公开(公告)号：US11864473B2

公开(公告)日：2024-01-02

申请号：US17404934

申请日：2021-08-17

Applicant: United Microelectronics Corp.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: G11C11/00 ,  H10N70/00 ,  H10B63/00

CPC classification number: H10N70/021 ,  H10B63/80 ,  H10N70/063 ,  H10N70/068 ,  H10N70/841 ,  H10N70/8833

Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.

公开(公告)号：US11862727B2

公开(公告)日：2024-01-02

申请号：US18090510

申请日：2022-12-29

Applicant: United Microelectronics Corp.

Inventor： Hao Che Feng ,  Hung Jen Huang ,  Hsin Min Han ,  Shih-Wei Su ,  Ming Shu Chiu ,  Pi-Hung Chuang ,  Wei-Hao Huang ,  Shao-Wei Wang ,  Ping Wei Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L29/7854 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/66818

Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

公开(公告)号：US20230420564A1

公开(公告)日：2023-12-28

申请号：US18244892

申请日：2023-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shou-Wan Huang ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L27/088 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L27/0688 ,  H01L29/0649 ,  H01L29/66795

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.