公开(公告)号：US09240355B2

公开(公告)日：2016-01-19

申请号：US14705397

申请日：2015-05-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/06

CPC classification number: H01L21/84 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1211 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/861

Abstract: An electrical device including a first conductivity semiconductor device present in a first semiconductor device region of an SOI substrate, and a second conductivity semiconductor device present in a second semiconductor device region of the SOI substrate. The electrical device also includes a diode present within a diode region of the SOI substrate that includes a first doped layer of a first conductivity semiconductor material that is present on an SOI layer of the SOI substrate. The first doped layer includes a first plurality of protrusions extending from a first connecting base portion. The semiconductor diode further includes a second doped layer of the second conductivity semiconductor material present over the first doped layer. The second doped layer including a second plurality of protrusions extending from a second connecting base portion. The second plurality of protrusions is present between and separating the first plurality of protrusions.

Abstract translation: 一种电气装置，包括存在于SOI衬底的第一半导体器件区域中的第一导电半导体器件和存在于SOI衬底的第二半导体器件区域中的第二导电半导体器件。 电子器件还包括存在于SOI衬底的二极管区域内的二极管，其包括存在于SOI衬底的SOI层上的第一导电半导体材料的第一掺杂层。 第一掺杂层包括从第一连接基部延伸的第一多个突起。 半导体二极管还包括存在于第一掺杂层上的第二导电半导体材料的第二掺杂层。 第二掺杂层包括从第二连接基部延伸的第二多个突起。 第二多个突起存在于并分离第一多个突起之间。

公开(公告)号：US20160005733A1

公开(公告)日：2016-01-07

申请号：US14855881

申请日：2015-09-16

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L27/088 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.

Abstract translation: 所公开的一个说明性装置尤其包括被隔离区隔开的第一和第二有源区，分别位于第一和第二有源区上方的第一和第二置换栅极结构以及位于隔离区上方的栅极配准结构 ，其中所述栅极配准结构包括位于所述隔离区域上方的绝缘材料层和抛光停止层，并且其中所述第一替换栅极结构的第一端表面邻接并接合所述栅极配准结构的第一侧表面， 第二替换栅极结构的端面邻接并接合栅极配准结构的第二侧表面。

公开(公告)号：US09224822B2

公开(公告)日：2015-12-29

申请号：US14023007

申请日：2013-09-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/20 ,  H01L21/36 ,  H01L29/36 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/36 ,  H01L21/02529 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: A layer of a silicon germanium alloy containing 30 atomic percent or greater germanium and containing substitutional carbon is grown on a surface of a semiconductor layer. The presence of the substitutional carbon in the layer of silicon germanium alloy compensates the strain of the silicon germanium alloy, and suppresses defect formation. Placeholder semiconductor fins are then formed to a desired dimension within the layer of silicon germanium alloy and the semiconductor layer. The placeholder semiconductor fins will relax for the most part, while maintaining strain in a lengthwise direction. An anneal is then performed which may either remove the substitutional carbon from each placeholder semiconductor fin or move the substitutional carbon into interstitial sites within the lattice of the silicon germanium alloy. Free-standing permanent semiconductor fins containing 30 atomic percent or greater germanium, and strain in the lengthwise direction are provided.

Abstract translation: 在半导体层的表面上生长含有30原子％以上的锗并含有取代碳的硅锗合金层。 硅锗合金层中的取代碳的存在补偿了硅锗合金的应变，并抑制了缺陷的形成。 然后将占位半导体散热片形成为硅锗合金层和半导体层内所需的尺寸。 占位半导体鳍片大部分放松，同时保持长度方向的应变。 然后进行退火，其可以从每个占位符半导体鳍去除取代的碳，或者将取代的碳移动到硅锗合金的晶格内的间隙位置。 提供含有30原子％以上的锗的独立的永久性半导体散热片，并且在长度方向上具有应变。

公开(公告)号：US20150372080A1

公开(公告)日：2015-12-24

申请号：US14839378

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Murat Kerem Akarvardar ,  Steven John Bentley ,  Kangguo Cheng ,  Bruce B. Doris ,  Jody Fronheiser ,  Ajey Poovannummoottil Jacob ,  Ali Khakifirooz ,  Toshiharu Nagumo

IPC: H01L29/06 ,  H01L27/092

CPC classification number: H01L29/0653 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract translation: 形成半导体结构的方法包括在第一组鳍片的翅片之间以及在第二组鳍片的翅片之间形成第一隔离区域。 第一组翅片形成在体半导体衬底中。 第二隔离区域形成在第一散热片组和第二散热片组之间，第二隔离区域延伸穿过第一隔离区域的一部分，使得第一隔离区域和第二隔离区域直接接触并且高于主体 第二隔离区域的半导体衬底大于第一隔离区域的体半导体衬底上方的高度。

公开(公告)号：US20150371892A1

公开(公告)日：2015-12-24

申请号：US14307902

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/308 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L21/76224 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/1029 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7853

Abstract: One method disclosed includes, among other things, forming an overall fin structure having a stepped cross-sectional profile, the fin structure having an upper part and a lower part positioned under the upper part, wherein the upper part has a first width and the lower part has a second width that is less than the first width, forming a layer of insulating material in trenches adjacent the overall fin structure such that the upper part of the overall fin structure and a portion of the lower part of the overall fin structure are exposed above an upper surface of the layer of insulating material, and forming a gate structure around the exposed upper part of the overall fin structure and the exposed portion of the lower part of the overall fin structure.

Abstract translation: 所公开的一种方法包括形成具有阶梯状横截面轮廓的整体翅片结构，翅片结构具有位于上部下方的上部和下部，其中上部具有第一宽度和下部 部分具有小于第一宽度的第二宽度，在邻近整个翅片结构的沟槽中形成绝缘材料层，使得整个翅片结构的上部和整个翅片结构的下部的一部分暴露 在绝缘材料层的上表面之上，并且围绕整个翅片结构的暴露的上部和整个翅片结构的下部的暴露部分形成栅极结构。

公开(公告)号：US09214567B2

公开(公告)日：2015-12-15

申请号：US14020096

申请日：2013-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/44 ,  H01L29/786 ,  H01L23/62 ,  H01L27/02

CPC classification number: H01L23/5256 ,  H01L23/5329 ,  H01L23/62 ,  H01L27/0288 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse is provided in one area of a semiconductor substrate. The E-fuse includes a vertical stack of from, bottom to top, base metal semiconductor alloy portion, a first metal semiconductor alloy portion, a second metal semiconductor portion, a third metal semiconductor alloy portion and a fourth metal semiconductor alloy portion, wherein the first metal semiconductor alloy portion and the third metal semiconductor portion have outer edges that are vertically offset and do not extend beyond vertical edges of the second metal semiconductor alloy portion and the fourth metal semiconductor alloy portion.

Abstract translation: 在半导体衬底的一个区域中设置电熔丝。 电子熔断器包括从底部到顶部的基底金属半导体合金部分，第一金属半导体合金部分，第二金属半导体部分，第三金属半导体合金部分和第四金属半导体合金部分的垂直堆叠，其中 第一金属半导体合金部分和第三金属半导体部分具有垂直偏移并且不延伸超过第二金属半导体合金部分和第四金属半导体合金部分的垂直边缘的外边缘。

公开(公告)号：US09190487B2

公开(公告)日：2015-11-17

申请号：US14283409

申请日：2014-05-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

公开(公告)号：US20150279742A1

公开(公告)日：2015-10-01

申请号：US14242046

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Michael Wedlake ,  Xiuyu Cai ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L21/8234 ,  H01L21/321 ,  H01L21/28 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/28017 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7833

Abstract: One method disclosed includes, among other things, forming a gate registration structure above an isolation region, wherein the gate registration structure comprises a plurality of layers of material, the uppermost layer of which is a polish-stop layer, forming first and second sacrificial gate structures above first and second active regions, respectively, wherein the first and second sacrificial gate structures abut and engage opposite sides of the gate registration structure, and performing at least one first chemical mechanical polishing (CMP) process to remove the gate cap layer so as to thereby expose a sacrificial gate electrode in each of the first and second sacrificial gate structures, wherein the uppermost layer of the gate registration structure serves as a polish-stop layer during the at least one first CMP process.

Abstract translation: 公开的一种方法包括在隔离区域之上形成栅极配准结构，其中栅极配准结构包括多层材料，其最上层是抛光停止层，形成第一和第二牺牲栅极 分别在第一和第二有源区域之上的结构，其中第一和第二牺牲栅极结构邻接并接合栅极对准结构的相对侧，并且执行至少一个第一化学机械抛光（CMP）工艺以移除栅极盖层，以便 从而在第一和第二牺牲栅极结构中的每一个中露出牺牲栅电极，其中栅极配准结构的最上层在至少一个第一CMP工艺期间用作抛光停止层。

公开(公告)号：US09142651B1

公开(公告)日：2015-09-22

申请号：US14226488

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/336 ,  H01L29/76 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/66537 ,  H01L21/2236 ,  H01L21/324 ,  H01L27/0886 ,  H01L29/1083 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/785

Abstract: One method disclosed includes, among other things, covering a top surface and a portion of the sidewalls of a fin with etch stop material, forming a sacrificial gate structure above and around the fin, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one process operation to remove the sacrificial gate structure and thereby define a replacement gate cavity, forming a counter-doped region in the fin below an upper surface of the fin and below the channel region of the device, wherein the counter-doped region is doped with a second type of dopant material that is of an opposite type relative to the first type of dopant material, and forming a replacement gate structure in the replacement gate cavity.

Abstract translation: 公开的一种方法包括用蚀刻停止材料覆盖翅片的顶表面和一部分侧壁，在翅片上方和周围形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔件， 至少一个处理操作以去除所述牺牲栅极结构，从而限定替换栅极腔，在所述鳍片的下表面以下且在所述器件的沟道区域下方形成鳍片中的反掺杂区域，其中所述反掺杂区域为 掺杂有相对于第一种掺杂剂材料相反类型的第二类型的掺杂剂材料，以及在替换栅极腔中形成替代栅极结构。

公开(公告)号：US20150255608A1

公开(公告)日：2015-09-10

申请号：US14200952

申请日：2014-03-07

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ajey P. Jacob ,  Witold P. Maszara ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming an initial fin structure comprised of portions of a substrate, a first epi semiconductor material and a second epi semiconductor material, forming a layer of insulating material so as to over-fill the trenches that define the fin, recessing a layer of insulating material such that a portion, but not all, of the second epi semiconductor portion of the final fin structure is exposed, forming a gate structure around the final fin structure, further recessing the layer of insulating material such that the first epi semiconductor material is exposed, removing the first epi semiconductor material to thereby define an under-fin cavity and substantially filling the under-fin cavity with a stressed material.

Abstract translation: 所公开的一种方法包括形成由衬底，第一外延半导体材料和第二外延半导体材料的部分组成的初始鳍结构，形成绝缘材料层，从而过度填充限定 翅片，使一层绝缘材料凹陷，使得最终翅片结构的第二外延半导体部分的一部分（但不是全部）暴露，围绕最终翅片结构形成栅极结构，进一步使绝缘材料层凹陷，使得 第一外延半导体材料被暴露，去除第一外延半导体材料，从而限定下鳍腔，并用受压材料基本上填充底鳍腔。