公开(公告)号：US06780695B1

公开(公告)日：2004-08-24

申请号：US10249563

申请日：2003-04-18

Applicant: Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

Inventor： Huajie Chen ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Gregory G. Freeman ,  David C. Ahlgren ,  David Angell ,  Kathryn T. Schonenberg ,  Kenneth J. Stein ,  Fen F. Jamin

IPC: H01L218238

CPC classification number: H01L21/8249 ,  H01L27/0623

Abstract: A method of forming a BiCMOS integrated circuit having a raised extrinsic base is provided. The method includes first forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate having device areas for forming at least one bipolar transistor and device areas for forming at least one complementary metal oxide semiconductor (CMOS) transistor. The polysilicon layer is then patterned to provide a sacrificial polysilicon layer over the device areas for forming the at least one bipolar transistor and its surrounding areas, while simultaneously providing at least one gate conductor in the device areas for forming at least one CMOS transistor. At least one pair of spacers are then formed about each of the at least one gate conductor and then a portion of the sacrificial polysilicon layer over the bipolar device areas are selectively removed to provide at least one opening in the bipolar device area. At least one bipolar transistor having a raised extrinsic base is then formed in the at least one opening.

Abstract translation: 提供一种形成具有凸起的外在基极的BiCMOS集成电路的方法。 该方法包括首先在位于具有用于形成至少一个双极晶体管的器件区域的衬底的顶部的栅极电介质的表面上方形成多晶硅层，以及用于形成至少一个互补金属氧化物半导体（CMOS）晶体管的器件区域）。 然后将多晶硅层图案化以在器件区域上提供用于形成至少一个双极晶体管及其周围区域的牺牲多晶硅层，同时在用于形成至少一个CMOS晶体管的器件区域中提供至少一个栅极导体。 然后围绕至少一个栅极导体的每一个形成至少一对间隔物，然后选择性地去除双极器件区域上的牺牲多晶硅层的一部分以在双极器件区域中提供至少一个开口。 然后在至少一个开口中形成至少一个具有凸起的非本征基极的双极晶体管。

公开(公告)号：US06750119B2

公开(公告)日：2004-06-15

申请号：US09838892

申请日：2001-04-20

Applicant: Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

Inventor： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC: H01L2120

CPC classification number: C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

公开(公告)号：US20090224772A1

公开(公告)日：2009-09-10

申请号：US12043169

申请日：2008-03-06

Applicant: Basanth Jagannathan ,  Zhenrong Jin ,  Hongmei Li

Inventor： Basanth Jagannathan ,  Zhenrong Jin ,  Hongmei Li

IPC: G01R35/00

CPC classification number: G01R27/32 ,  G01R35/00

Abstract: S-parameter data is measured on an embedded device test structure, an open dummy, and a short dummy. A 4-port network of the pad set parasitics of the embedded device test structure is modeled by a parameterized netlist containing a lumped element network having at least one parameterized lumped element. The S-parameter data across a range of measurement frequencies is fitted with the parametrized netlist employing the at least one parameterized lumped element as at least one fitting parameter for the S-parameter data. Thus, the fitting method is a multi-frequency fitting for the at least one parameterized lumped element. A 4-port Y-parameter (admittance parameter) is obtained from the fitted parameterized netlist. The Y-parameter of the device under test is obtained from the measured admittance of the embedded device test structure and the calculated 4-port Y parameter.

Abstract translation: S参数数据是在嵌入式设备测试结构上测量的，一个开放虚拟的和一个短虚拟的。 嵌入式设备测试结构的焊盘组寄生效应的4端口网络由包含具有至少一个参数化集总元件的集总元件网络的参数化网表建模。 将测量频率范围内的S参数数据与采用至少一个参数化集总元件的参数化网表拟合为S参数数据的至少一个拟合参数。 因此，拟合方法是用于至少一个参数化的集总元件的多频率拟合。 从拟合的参数化网表获得4端口Y参数（导纳参数）。 被测器件的Y参数是从嵌入式器件测试结构的测量导纳和计算的4端口Y参数获得的。

公开(公告)号：US20080124881A1

公开(公告)日：2008-05-29

申请号：US11562735

申请日：2006-11-22

Applicant: Jack Ooh Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

Inventor： Jack Ooh Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC: H01L21/331

CPC classification number: H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract translation: 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

公开(公告)号：US20060255415A1

公开(公告)日：2006-11-16

申请号：US10908448

申请日：2005-05-12

Applicant: Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

Inventor： Gregory Freeman ,  Anil Chinthakindi ,  David Greenberg ,  Basanth Jagannathan ,  Marwan Khater ,  John Pekarik ,  Xudong Wang

IPC: H01L29/76

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7843

Abstract: A field effect transistor is provided which includes a contiguous single-crystal semiconductor region in which a source region, a channel region and a drain region are disposed. The channel region has an edge in common with the source region as a source edge, and the channel region further has an edge in common with the drain region as a drain edge. A gate conductor overlies the channel region. The field effect transistor further includes a structure which applies a stress at a first magnitude to only one of the source edge and the drain edge while applying the stress at no greater than a second magnitude to another one of the source edge and the drain edge, wherein the second magnitude has a value ranging from zero to about half the first magnitude. In a particular embodiment, the stress is applied at the first magnitude to the source edge while the zero or lower magnitude stress is applied to the drain edge. In another embodiment, the stress is applied at the first magnitude to the drain edge while the zero or lower magnitude stress is applied to the drain edge.

Abstract translation: 提供一种场效应晶体管，其包括其中设置有源极区，沟道区和漏极区的邻接单晶半导体区。 沟道区域具有与源极区域共同的边缘作为源极边缘，并且沟道区域还具有与作为漏极边缘的漏极区域共同的边缘。 栅极导体覆盖沟道区域。 场效应晶体管还包括将源极边缘和漏极边缘的另一个施加不大于第二幅度的应力的第一幅度的应力仅施加到源极边缘和漏极边缘中的一个的结构， 其中所述第二幅度具有从零到所述第一幅度的大约一半的值。 在特定实施例中，将应力以第一幅度施加到源极边缘，同时零或较小幅度应力施加到漏极边缘。 在另一个实施例中，将应力以第一幅度施加到漏极边缘，同时将零或较小的幅度应力施加到漏极边缘。

公开(公告)号：US06927476B2

公开(公告)日：2005-08-09

申请号：US09962738

申请日：2001-09-25

Applicant: Gregory G. Freeman ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Kathryn T. Schonenberg ,  Shwu-Jen Jeng ,  Kenneth J. Stein ,  Jeffrey B. Johnson

Inventor： Gregory G. Freeman ,  Seshadri Subbanna ,  Basanth Jagannathan ,  Kathryn T. Schonenberg ,  Shwu-Jen Jeng ,  Kenneth J. Stein ,  Jeffrey B. Johnson

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/737 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

Abstract: A raised extrinsic base, silicon germanium (SiGe) heterojunction bipolar transistor (HBT), and a method of making the same is disclosed herein. The heterojunction bipolar transistor includes a substrate, a silicon germanium layer formed on the substrate, a collector layer formed on the substrate, a raised extrinsic base layer formed on the silicon germanium layer, and an emitter layer formed on the silicon germanium layer. The silicon germanium layer forms a heterojunction between the emitter layer and the raised extrinsic base layer. The bipolar transistor further includes a base electrode formed on a portion of the raised extrinsic base layer, a collector electrode formed on a portion of the collector layer, and an emitter electrode formed on a portion of the emitter layer. Thus, the heterojunction bipolar transistor includes a self-aligned raised extrinsic base, a minimal junction depth, and minimal interstitial defects influencing the base width, all being formed with minimal thermal processing. The heterojunction bipolar transistor simultaneously improves three factors that affect the speed and performance of bipolar transistors: base width, base resistance, and base-collector capacitance.

Abstract translation: 本文公开了一种凸起的外在基极，硅锗（SiGe）异质结双极晶体管（HBT）及其制造方法。 异质结双极晶体管包括基板，形成在基板上的硅锗层，形成在基板上的集电极层，形成在硅锗层上的升高的非本征基极层和形成在硅锗层上的发射极层。 硅锗层在发射极层和凸起的非本征基极层之间形成异质结。 双极晶体管还包括形成在凸起的非本征基极层的一部分上的基极，在集电极层的一部分上形成的集电极，以及形成在发射极层的一部分上的发射极。 因此，异质结双极晶体管包括自对准凸起的外在基极，最小结深度以及影响基底宽度的最小间隙缺陷，全部以最小的热处理形成。 异质结双极晶体管同时改善了影响双极晶体管速度和性能的三个因素：基极宽度，基极电阻和基极集电极电容。

公开(公告)号：US06908866B2

公开(公告)日：2005-06-21

申请号：US10775515

申请日：2004-02-10

Applicant: Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

Inventor： Jack Oon Chu ,  Basanth Jagannathan ,  Alfred Grill ,  Bernard Steele Meyerson ,  John Albrecht Ott

IPC: C23C16/32 ,  C30B25/02 ,  H01L21/31 ,  H01L21/469

CPC classification number: C23C16/325 ,  C23C16/32 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/12674

Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon

Abstract translation: 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些外延SiC和SiGeC膜是原位掺杂的p型或n型，并且存在低浓度的碳<20 20 -3 -3， 生长的p型或n型掺杂物分布可以承受炉退火至850℃的温度和快速热退火温度至1000℃

公开(公告)号：US20050054171A1

公开(公告)日：2005-03-10

申请号：US10953378

申请日：2004-09-29

Applicant: Jack Chu ,  Douglas Coolbaugh ,  James Dunn ,  David Greenberg ,  David Harame ,  Basanth Jagannathan ,  Robb Johnson ,  Louis Lanzerotti ,  Kathryn Schonenberg ,  Ryan Wuthrich

Inventor： Jack Chu ,  Douglas Coolbaugh ,  James Dunn ,  David Greenberg ,  David Harame ,  Basanth Jagannathan ,  Robb Johnson ,  Louis Lanzerotti ,  Kathryn Schonenberg ,  Ryan Wuthrich

IPC: H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC classification number: H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract translation: 提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

公开(公告)号：US06858532B2

公开(公告)日：2005-02-22

申请号：US10316211

申请日：2002-12-10

Applicant: Wesley C. Natzle ,  David C. Ahlgren ,  Steven G. Barbee ,  Marc W. Cantell ,  Basanth Jagannathan ,  Louis D. Lanzerotti ,  Seshadri Subbanna ,  Ryan W. Wuthrich

Inventor： Wesley C. Natzle ,  David C. Ahlgren ,  Steven G. Barbee ,  Marc W. Cantell ,  Basanth Jagannathan ,  Louis D. Lanzerotti ,  Seshadri Subbanna ,  Ryan W. Wuthrich

IPC: H01L21/302 ,  H01L21/311 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/732 ,  H01L21/4763

CPC classification number: H01L29/66242 ,  H01L21/31116 ,  H01L21/8249

Abstract: An oxide etch process is described which may be used for emitter and base preparation in bipolar SiGe devices. The low temperature process employed produces electrical insulation between the emitter and base by a COR etch which preserves insulating TEOS glass. The insulating TEOS glass provides reduced capacitance and helps to achieve high speed. An apparatus is also described for practicing the disclosed process.

Abstract translation: 描述了氧化物蚀刻工艺，其可用于双极SiGe器件中的发射极和基极准备。 所采用的低温工艺通过保留绝缘TEOS玻璃的COR蚀刻产生发射极和基极之间的电绝缘。 绝缘TEOS玻璃提供降低的电容并有助于实现高速度。 还描述了用于实施所公开的方法的装置。

公开(公告)号：US06780735B2

公开(公告)日：2004-08-24

申请号：US09843783

申请日：2001-04-30

Applicant: Basanth Jagannathan ,  Jack O. Chu ,  Ryan W. Wuthrich ,  Byeongju Park

Inventor： Basanth Jagannathan ,  Jack O. Chu ,  Ryan W. Wuthrich ,  Byeongju Park

IPC: H01L2104

CPC classification number: C30B29/06 ,  C30B25/02 ,  C30B29/08 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02579 ,  H01L21/0262

Abstract: We provide a method of doping an Si or SiGe film with carbon or boron. By reducing the silicon precursor pressure, heavily-doped films may be obtained. A single dopant source may be used. The doped Si and SiGe films are of suitable quality for use in a transistor such as an HBT.

Abstract translation: 我们提供了用碳或硼掺杂Si或SiGe膜的方法。 通过降低硅前体压力，可以获得重掺杂的膜。 可以使用单个掺杂剂源。 掺杂的Si和SiGe膜具有适用于诸如HBT之类的晶体管的质量。