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11.发明申请FLASH MEMORY DEVICES AND PROGRAMMING METHODS THAT VARY PROGRAMMING CONDITIONS IN RESPONSE TO A SELECTED STEP INCREMENT 有权闪存存储器件和编程方法，其中对于选择的阶段增量的响应的变化的编程条件公开(公告)号：US20090003075A1
公开(公告)日：2009-01-01
申请号：US12134648
申请日：2008-06-06
Applicant: In-Mo Kim , Jae-Yong Jeong , Chi-Weon Yoon
Inventor： In-Mo Kim , Jae-Yong Jeong , Chi-Weon Yoon
IPC: G11C16/06
CPC classification number: G11C16/10
Abstract: A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.
Abstract translation: 一种闪速存储器件包括：闪存单元阵列，具有布置有字线和位线的闪速存储器单元;字线驱动器电路，被配置为在编程操作期间以选定的阶跃增量驱动所述字线，所述体电压电源电路被配置为 将大容量电压提供到闪存单元阵列的大部分中;以及写入电路，其被配置为驱动在编程操作期间由条件选择的位线。 控制逻辑块被配置为在编程操作期间控制写入电路和体电压电源电路。 控制逻辑块被配置为使得写入电路和/或体电压电源电路响应于所选择的步进增量来改变写入电路和/或体电压的条件中的至少一个。
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12.发明申请Flash memory device having a verify data buffer capable of being employed as a program data buffer, and a method thereof 有权具有能够被用作程序数据缓冲器的验证数据缓冲器的闪速存储器件及其方法公开(公告)号：US20080170443A1
公开(公告)日：2008-07-17
申请号：US12003589
申请日：2007-12-28
Applicant: Kee-ho Jung , Jae-yong Jeong , Chi-weon Yoon
Inventor： Kee-ho Jung , Jae-yong Jeong , Chi-weon Yoon
IPC: G11C16/06
CPC classification number: G11C16/3454
Abstract: A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.
Abstract translation: 闪速存储器件包括被配置为缓冲要在存储器单元阵列中编程的程序数据的程序数据缓冲器，以及配置为比较验证数据以确认程序数据是否被精确地编程在存储单元阵列中的校验数据缓冲器，其中， 验证数据缓冲器的至少一部分被有选择地启用为响应于缓冲器控制信号的验证数据缓冲器或程序数据缓冲器。
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13.发明授权公开(公告)号：US09798659B2
公开(公告)日：2017-10-24
申请号：US14837857
申请日：2015-08-27
Applicant: Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
Inventor： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
CPC classification number: G06F12/0646 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F2212/2022 , G11C5/025 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483
Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
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公开(公告)号：US09355721B2
公开(公告)日：2016-05-31
申请号：US14800727
申请日：2015-07-16
Applicant: Chi-Weon Yoon , Hyun-Kook Park , Dae-Seok Byeon
Inventor： Chi-Weon Yoon , Hyun-Kook Park , Dae-Seok Byeon
CPC classification number: G11C13/0069 , G11C7/04 , G11C11/1675 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C2013/0071 , G11C2013/0083 , G11C2013/0092
Abstract: A method of operating a memory device includes; applying a pre-write voltage to a selected memory cell by applying a first voltage to a first signal line connected to the selected memory cell and a second voltage to a second signal line connected to the selected memory cell during a first set writing interval, wherein a level of the first voltage is higher than a level of the second voltage, and thereafter, applying a write voltage to the selected memory cell by applying a third voltage having a level lower than the level of the first voltage and higher than the level of the second voltage to the first signal line during a second set writing interval.
Abstract translation: 操作存储器件的方法包括： 通过在连接到所选存储单元的第一信号线上施加第一电压并将第二电压施加到在第一设定写入间隔期间连接到所选存储单元的第二信号线，将预写电压施加到所选择的存储单元，其中 所述第一电压的电平高于所述第二电压的电平，然后通过施加具有低于所述第一电压的电平的电平的第三电压并高于所述第一电压的电平而对所选择的存储单元施加写入电压 在第二设定写入间隔期间到第一信号线的第二电压。
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15.发明申请CROSS-POINT MEMORY DEVICE INCLUDING MULTI-LEVEL CELLS AND OPERATING METHOD THEREOF 有权包括多级细胞的交叉点记忆装置及其操作方法公开(公告)号：US20160148678A1
公开(公告)日：2016-05-26
申请号：US14800060
申请日：2015-07-15
Applicant: HYUN-KOOK PARK , CHI-WEON YOON , DAE-SEOK BYEON
Inventor： HYUN-KOOK PARK , CHI-WEON YOON , DAE-SEOK BYEON
CPC classification number: G11C13/004 , G11C11/1659 , G11C11/1673 , G11C11/56 , G11C11/5607 , G11C11/5642 , G11C13/0002 , G11C2013/0054 , G11C2213/71
Abstract: A method of operating a cross-point memory device, having an array of multilevel cells, includes performing a first reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a first state and performing a second reading operation with respect to the multilevel cells through a plurality of sensing operations to determine a second state. A difference between a level of a first voltage used in a first sensing operation and a level of a second voltage used in a second sensing operation in the first reading operation is different from a difference between a level of a third voltage used in a first sensing operation and a level of a fourth voltage used in a second sensing operation in the second reading operation.
Abstract translation: 一种操作具有多电平单元阵列的交叉点存储器件的方法包括通过多个感测操作执行关于多电平单元的第一读取操作，以确定第一状态并执行关于第二读取操作的第二读取操作 所述多电平单元通过多个感测操作来确定第二状态。 在第一读取操作中使用的第一电压的电平与在第一读取操作中的第二感测操作中使用的第二电压的电平之间的差异不同于在第一感测中使用的第三电压的电平之间的差 操作和在第二读取操作中的第二感测操作中使用的第四电压的电平。
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Patent Agency Ranking
公开(公告)号：US20160027485A1
公开(公告)日：2016-01-28
申请号：US14683186
申请日：2015-04-10
Applicant: HYUN-KOOK PARK , YEONG-TAEK LEE , DAE-SEOK BYEON , CHI-WEON YOON
Inventor： HYUN-KOOK PARK , YEONG-TAEK LEE , DAE-SEOK BYEON , CHI-WEON YOON
CPC classification number: G11C7/22 , G06F11/073 , G06F11/076 , G11C7/062 , G11C7/067 , G11C7/1045 , G11C7/12 , G11C7/14 , G11C11/5642 , G11C13/004 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/42 , G11C29/52 , G11C2013/0054 , G11C2213/72
Abstract: A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region.
Abstract translation: 一种操作存储器系统的方法，包括：存储单元阵列中包含共同连接到第一信号线的存储单元; 根据单元区域划分存储单元，并且使用从多个读取参考中选择并且分别对应于每个单元区域的读取参考，独立地对设置在每个单元区域中的存储单元执行读取操作。
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17.发明授权Memory devices for reducing boosting charge leakage and systems including the same 有权用于减少增加电荷泄漏的存储器件及包括其的系统公开(公告)号：US09036425B2
公开(公告)日：2015-05-19
申请号：US13229107
申请日：2011-09-09
Applicant: Chi Weon Yoon , Sang-Wan Nam , Dong Hyuk Chae
Inventor： Chi Weon Yoon , Sang-Wan Nam , Dong Hyuk Chae
CPC classification number: G11C16/0483 , G11C16/3418
Abstract: A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array.
Abstract translation: 三维（3D）非易失性存储器包括存储单元阵列和合并驱动器，其被配置为将相同电平的合并电压施加到存储单元阵列中的公共源线和体。
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18.发明申请Address Scheduling Methods For Non-Volatile Memory Devices With Three-Dimensional Memory Cell Arrays 审中-公开用于具有三维存储器单元阵列的非易失性存储器件的地址调度方法公开(公告)号：US20120047321A1
公开(公告)日：2012-02-23
申请号：US13213806
申请日：2011-08-19
Applicant: Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
Inventor： Chi Weon Yoon , Dong Hyuk Chae , Sang-Wan Nam , Jung-Yun Yun
CPC classification number: G06F12/0646 , G06F3/0619 , G06F3/0653 , G06F3/0679 , G06F2212/2022 , G11C5/025 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483
Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.
Abstract translation: 至少一个地址调度方法包括选择第一位线，选择连接到第一位线的第一串，在第一串中的每个多电平单元的N页上从底部字线到顶部执行地址调度 字线，并且在完成第一串中的所有字线上的地址调度之后，以与对第一字符串执行的相同的方式依次执行第二至第K个字符串的地址调度，其中“k”为2或 自然数大于2。
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19.发明申请NON-VOLATILE MEMORY DEVICE AND METHOD FOR PROGRAMMING THE DEVICE, AND MEMORY SYSTEM 有权非易失性存储器件和用于编程器件和存储器系统的方法公开(公告)号：US20120039120A1
公开(公告)日：2012-02-16
申请号：US13157344
申请日：2011-06-10
Applicant: Chi-Weon YOON , Dong-Hyuk CHAE , Sang-Wan NAM , Sung-Won YUN
Inventor： Chi-Weon YOON , Dong-Hyuk CHAE , Sang-Wan NAM , Sung-Won YUN
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/3418
Abstract: A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer.
Abstract translation: 一种非易失性存储器件包括存储单元阵列，该存储单元阵列包括连接到相应的字线和连接到相应位线的列的行中的存储单元，存储程序数据的页缓冲器，用于编程和重新编程的读写电路 将程序数据写入到存储单元阵列的选择的存储单元中，并从编程的存储器单元中读取存储的数据;以及控制电路，其控制页面缓冲器和读写电路，以通过从其中加载程序数据对所选存储单元进行编程 页面缓冲区，并通过重新加载页面缓冲区中的程序数据来重新编程所选择的存储单元。
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20.发明授权公开(公告)号：US07539077B2
公开(公告)日：2009-05-26
申请号：US11775872
申请日：2007-07-11
Applicant: Chi-Weon Yoon , Heung-Soo Lim
Inventor： Chi-Weon Yoon , Heung-Soo Lim
IPC: G11C8/00
CPC classification number: G11C7/1078 , G11C7/1087 , G11C7/1096 , G11C16/06
Abstract: A flash memory device includes a memory cell array with multiple memory cells, a data buffer, a write driver and a controller. The data buffer stores data to be programmed into the memory cells, the data having sequential data addresses. The write driver programs the data stored in the data buffer into the memory cells during one programming operation. The controller controls operations of the data buffer and the write driver, and performs flexible mapping between addresses of the data buffer and the data addresses based on a first address of the data.
Abstract translation: 闪存器件包括具有多个存储器单元的存储单元阵列，数据缓冲器，写入驱动器和控制器。 数据缓冲器将要编程的数据存储到存储器单元中，数据具有顺序数据地址。 写入驱动器在一个编程操作期间将存储在数据缓冲器中的数据编程到存储器单元中。 控制器控制数据缓冲器和写入驱动器的操作，并且基于数据的第一地址在数据缓冲器的地址和数据地址之间执行灵活的映射。
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