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    Silicon phosphor electroluminescence device with nanotip electrode
    11.
    发明申请
    Silicon phosphor electroluminescence device with nanotip electrode 有权
    具有纳米尖电极的硅荧光体电致发光器件

    公开(公告)号：US20060180817A1

    公开(公告)日：2006-08-17

    申请号：US11061946

    申请日：2005-02-17

    Applicant: Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

    Inventor： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

    IPC: H01L27/15

    CPC classification number: H05B33/145

    Abstract: An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

    Abstract translation: 提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。 该方法包括：形成具有纳米尖端的底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。 纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。 通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。 在一个方面，Si磷光体层是SRSO层。 响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

    Iridium oxide nanostructure
    12.
    发明授权
    Iridium oxide nanostructure 有权
    氧化铱纳米结构

    公开(公告)号：US07053403B1

    公开(公告)日：2006-05-30

    申请号：US11339876

    申请日：2006-01-26

    Applicant: Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

    Inventor： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

    IPC: H01L29/10 ,  H01L29/12

    CPC classification number: H01L21/31111 ,  B81C1/00111 ,  B82Y10/00

    Abstract: A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.

    Abstract translation: 提供了用于构图氧化铱（IrOx）纳米结构的方法。 该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。 通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。 例如，第一种材料可以是难熔金属或难熔金属氧化物。 第二种材料可以是SiOx。 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。

    Iridium oxide nanostructure patterning
    14.
    发明授权
    Iridium oxide nanostructure patterning 有权
    氧化铱纳米结构图案

    公开(公告)号：US07022621B1

    公开(公告)日：2006-04-04

    申请号：US11013804

    申请日：2004-12-15

    Applicant: Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

    Inventor： Fengyan Zhang ,  Gregory M. Stecker ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

    IPC: H01L21/461

    CPC classification number: H01L21/31111 ,  B81C1/00111 ,  B82Y10/00

    Abstract: A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.

    Abstract translation: 提供了用于构图氧化铱（IrOx）纳米结构的方法。 该方法包括：在第二区域附近形成衬底第一区域; 从覆盖第一区域的连续IrOx膜生长IrOx纳米结构; 同时从覆盖第二区域的非连续IrOx膜生长IrOx纳米结构; 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域; 并提升覆盖第二区域的IrOx纳米结构。 通常，第一区域由第一材料形成，第二区域由不同于第一材料的第二材料形成。 例如，第一种材料可以是难熔金属或难熔金属氧化物。 第二种材料可以是SiOx。 选择性地蚀刻由非连续IrOx膜暴露的第二区域的区域的步骤包括将衬底暴露于与IrOx比第二材料更具反应性的蚀刻剂。

    Pt/PGO etching process for FeRAM applications
    15.
    发明申请
    Pt/PGO etching process for FeRAM applications 失效

    公开(公告)号：US20060040413A1

    公开(公告)日：2006-02-23

    申请号：US10923381

    申请日：2004-08-20

    Applicant: Fengyan Zhang ,  Bruce Ulrich ,  Lisa Stecker ,  Sheng Hsu

    Inventor： Fengyan Zhang ,  Bruce Ulrich ,  Lisa Stecker ,  Sheng Hsu

    IPC: H01L21/00

    CPC classification number: H01L21/32139 ,  H01L21/32136 ,  H01L27/1085 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

    Abstract: A method of etching a noble metal top electrode on a ferroelectric layer while preserving the ferroelectric properties of the ferroelectric layer and removing etching residue includes preparing a substrate; depositing a barrier layer on the substrate; depositing a bottom electrode layer on the barrier layer; depositing a ferroelectric layer on the bottom electrode layer; depositing a noble metal top electrode layer on the ferroelectric layer; depositing an adhesion layer on the top electrode layer; depositing a hard mask layer on the adhesion layer; patterning the hard mask; etching the noble metal top electrode layer in an initial etching step at a predetermined RF bias power, which produces etching residue; and over etching the noble metal top electrode layer and ferroelectric layer at an RF bias power lower than that of the predetermined RF bias power to remove etching residue from the initial etching step.

    Memory cell with an asymmetrical area
    16.
    发明申请
    Memory cell with an asymmetrical area 有权
    具有不对称区域的存储单元

    公开(公告)号：US20050243630A1

    公开(公告)日：2005-11-03

    申请号：US11174034

    申请日：2005-07-01

    Applicant: Sheng Hsu ,  Fengyan Zhang

    Inventor： Sheng Hsu ,  Fengyan Zhang

    IPC: H01L21/28 ,  G11C11/15 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8239 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/105 ,  H01L27/115 ,  H01L27/22 ,  H01L27/24 ,  H01L29/68 ,  H01L43/08 ,  H01L45/00 ,  G11C7/00

    CPC classification number: H01L27/105 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/52 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

    Abstract: An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method comprises: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.

    Abstract translation: 提供了一种不对称区域存储单元和用于形成非对称区域存储单元的制造方法。 该方法包括：形成具有面积的底部电极; 形成覆盖在底部电极上的具有不对称区域的CMR存储膜; 并且形成覆盖CMR膜的具有小于底部电极区域的面积的顶部电极。 在一个方面，CMR膜具有邻近顶部电极的第一区域和与底部电极相邻的大于第一区域的第二区域。 通常，尽管CMR膜的第二区域可能小于底部电极区域，但是CMR膜的第一区域大致等于顶部电极区域。

    Asymmetric-area memory cell
    18.
    发明申请
    Asymmetric-area memory cell 有权
    非对称区记忆单元

    公开(公告)号：US20050124112A1

    公开(公告)日：2005-06-09

    申请号：US10730726

    申请日：2003-12-08

    Applicant: Sheng Hsu ,  Fengyan Zhang

    Inventor： Sheng Hsu ,  Fengyan Zhang

    IPC: H01L21/28 ,  G11C11/15 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8239 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/105 ,  H01L27/115 ,  H01L27/22 ,  H01L27/24 ,  H01L29/68 ,  H01L43/08 ,  H01L45/00 ,  H01L21/8242

    CPC classification number: H01L27/105 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/52 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

    Abstract: An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method comprises: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.

    Abstract translation: 提供了一种不对称区域存储单元和用于形成非对称区域存储单元的制造方法。 该方法包括：形成具有面积的底部电极; 形成覆盖在底部电极上的具有不对称区域的CMR存储膜; 并且形成覆盖CMR膜的具有小于底部电极区域的面积的顶部电极。 在一个方面，CMR膜具有邻近顶部电极的第一区域和与底部电极相邻的大于第一区域的第二区域。 通常，尽管CMR膜的第二区域可能小于底部电极区域，但是CMR膜的第一区域大致等于顶部电极区域。

    Method for making single-phase c-axis doped PGO ferroelectric thin films
    19.
    发明授权
    Method for making single-phase c-axis doped PGO ferroelectric thin films 失效
    制备单相c轴掺杂PGO铁电薄膜的方法

    公开(公告)号：US06897074B1

    公开(公告)日：2005-05-24

    申请号：US10794736

    申请日：2004-03-03

    Applicant: Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

    Inventor： Fengyan Zhang ,  Wei-Wei Zhuang ,  Jong-Jan Lee ,  Sheng Teng Hsu

    IPC: H01L21/00 ,  H01L21/02 ,  H01L21/316 ,  H01L41/22

    CPC classification number: H01L21/31691 ,  H01L28/55 ,  H01L41/317

    Abstract: A method for forming a doped PGO ferroelectric thin film, and related doped PGO thin film structures are described. The method comprising: forming either an electrically conductive or electrically insulating substrate; forming a doped PGO film overlying the substrate; annealing; crystallizing; and, forming a single-phase c-axis doped PGO thin film overlying the substrate, having a Curie temperature of greater than 200 degrees C. Forming a doped PGO film overlying the substrate includes depositing a doped precursor in the range between 0.1N and 0.5N, with a molecular formula of Pby-xMxGe3O11, where: M is a doping element; y=4.5 to 6; and, x=0.1 to 1. The element M can be Sn, Ba, Sr, Cd, Ca, Pr, Ho, La, Sb, Zr, or Sm.

    Abstract translation: 描述了用于形成掺杂的PGO铁电薄膜的方法以及相关的掺杂PGO薄膜结构。 该方法包括：形成导电或电绝缘的衬底; 在衬底上形成掺杂的PGO膜; 退火; 结晶 并且形成覆盖在衬底上的单相c轴掺杂的PGO薄膜，其居里温度大于200℃。形成覆盖在衬底上的掺杂PGO膜包括沉积在0.1N和0.5之间的掺杂前体 N，具有分子式为Pb x Si x N x N x O 11，其中：M是掺杂物 元件; y = 4.5〜6; x = 0.1〜1。元素M可以是Sn，Ba，Sr，Cd，Ca，Pr，Ho，La，Sb，Zr或Sm。

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