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    MEMORY DEVICE, SYSTEMS AND DEVICES INCLUDING A MEMORY DEVICE, METHODS OF OPERATING A MEMORY DEVICE, AND/OR METHODS OF OPERATING SYSTEMS AND DEVICES INCLUDING A MEMORY DEVICE
    11.
    发明申请
    MEMORY DEVICE, SYSTEMS AND DEVICES INCLUDING A MEMORY DEVICE, METHODS OF OPERATING A MEMORY DEVICE, AND/OR METHODS OF OPERATING SYSTEMS AND DEVICES INCLUDING A MEMORY DEVICE 有权
    存储器件，包括存储器件的系统和器件，操作存储器件的方法和/或操作系统的方法和包括存储器件的器件

    公开(公告)号：US20120039132A1

    公开(公告)日：2012-02-16

    申请号：US13094382

    申请日：2011-04-26

    申请人： Byung Jun Min ,  Hoi Ju Chung

    发明人： Byung Jun Min ,  Hoi Ju Chung

    IPC分类号： G11C7/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2013/0088 ,  G11C2213/71

    摘要： In one embodiment, a memory device includes a plurality of unit cell arrays. Each unit cell array includes an array of memory cells arranged in a plurality of columns, and each column is associated with a bit line. The memory device further includes a program control circuit configured to program cells in the plurality of unit cell arrays based on program bits associated with the plurality of unit cell arrays. For example, the program control unit is configured to simultaneously program one memory cell in each unit cell array having at least one associated program bit.

    摘要翻译： 在一个实施例中，存储器件包括多个单元阵列。 每个单元阵列包括布置在多个列中的存储单元的阵列，并且每列与位线相关联。 存储装置还包括程序控制电路，其被配置为基于与多个单元阵列相关联的程序位对多个单元阵列中的单元进行编程。 例如，程序控制单元被配置为同时对具有至少一个关联程序位的每个单位单元阵列中的一个存储单元进行编程。

    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
    12.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME 有权
    半导体存储器件和存储器系统，包括它们

    公开(公告)号：US20160042809A1

    公开(公告)日：2016-02-11

    申请号：US14798634

    申请日：2015-07-14

    申请人： Young-Il KIM ,  Hoi-ju CHUNG

    发明人： Young-Il KIM ,  Hoi-ju CHUNG

    IPC分类号： G11C29/42 ,  G11C29/44 ,  G11C29/36

    CPC分类号： G11C29/42 ,  G11C11/401 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0411

    摘要： A semiconductor memory device includes a memory cell array, an input/output (I/O) gating circuit, an error decision circuit and an error check and correction (ECC) circuit. The I/O gating circuit reads test pattern data to provide test result data in a test mode and reads a codeword in a normal mode. The error decision circuit determines the correctability of errors in the test result data by a first unit, based on the test pattern data and the test result data and provides a first error kind signal indicating a first determination result, in the test mode. The ECC circuit decodes the codeword including main data and parity data generated based on the main, determines correctability of errors in the codeword by a second unit and provides a second error kind signal indicating a second determination result, in the normal mode. The main data includes a plurality of unit data.

    摘要翻译： 半导体存储器件包括存储单元阵列，输入/输出（I / O）选通电路，错误判定电路和错误校验（ECC）电路。 I / O门控电路读取测试模式数据，以便在测试模式下提供测试结果数据，并以正常模式读取码字。 错误判定电路基于测试图形数据和测试结果数据，确定第一单元在测试结果数据中的错误的可校正性，并且在测试模式中提供指示第一确定结果的第一错误种类信号。 ECC电路对包括主数据和基于主数据生成的奇偶校验数据的码字进行解码，由第二单元确定码字中的错误的可校正性，并在正常模式下提供指示第二确定结果的第二错误种类信号。 主数据包括多个单位数据。

    NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT
    14.
    发明申请
    NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT 有权
    使用可变电阻元件的非易失性存储器件

    公开(公告)号：US20110267876A1

    公开(公告)日：2011-11-03

    申请号：US13085453

    申请日：2011-04-12

    申请人： Byung-Jun MIN ,  Hoi-Ju CHUNG

    发明人： Byung-Jun MIN ,  Hoi-Ju CHUNG

    IPC分类号： G11C11/00 ,  G11C29/04

    CPC分类号： G11C8/12 ,  G11C13/0004 ,  G11C29/80 ,  G11C29/846

    摘要： A nonvolatile memory device that employs a variable resistive element includes: a memory cell array having a plurality of memory cells; a first circuit block that is disposed at one side of the memory cell array and performs a first operation on the memory cells; a second circuit block that is disposed at the other side of the memory cell array and performs a second operation on the memory cells, wherein the second operation is different from the first operation; and a redundancy block that is disposed closer to the second circuit block than the first circuit block, and which compares a repair address of a repaired memory cell among the plurality of memory cells with an input address to then generate a redundancy control signal, and to supply the redundancy control signal to the first circuit block and the second circuit block.

    摘要翻译： 采用可变电阻元件的非易失性存储器件包括：具有多个存储单元的存储单元阵列; 第一电路块，设置在所述存储单元阵列的一侧，并对所述存储单元执行第一操作; 第二电路块，设置在存储单元阵列的另一侧，并对存储单元执行第二操作，其中第二操作与第一操作不同; 以及与第一电路块相比更靠近第二电路块设置的冗余块，并且将多个存储单元中的修复存储单元的修复地址与输入地址进行比较，然后生成冗余控制信号，并且 将冗余控制信号提供给第一电路块和第二电路块。

    SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM HAVING THE SAME, AND METHOD FOR OPERATING THE SEMICONDUCTOR DEVICE
    15.
    发明申请
    SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM HAVING THE SAME, AND METHOD FOR OPERATING THE SEMICONDUCTOR DEVICE 有权
    半导体器件，具有该半导体器件的半导体器件，以及用于操作半导体器件的方法

    公开(公告)号：US20110261615A1

    公开(公告)日：2011-10-27

    申请号：US13073021

    申请日：2011-03-28

    申请人： Joon-Yong CHOI ,  Hoi Ju CHUNG

    发明人： Joon-Yong CHOI ,  Hoi Ju CHUNG

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2013/0085 ,  G11C2213/72

    摘要： A semiconductor device includes phase-change memory cells and an access circuit. The access circuit generates a plurality of bitwise comparison signals indicating different comparison events for respective write and read bit groups. At least a portion of the write data is then written to the phase-change memory cells according to a number of activated comparison signals for each comparison event, as well as according to a ratio of a set current pulse width and a reset current pulse width as applied to the of phase-change memory cells.

    摘要翻译： 半导体器件包括相变存储单元和存取电路。 存取电路产生多个按比特比较信号，指示不同比较事件的各个写和读位组。 然后根据用于每个比较事件的激活的比较信号的数量，以及根据设定的电流脉冲宽度和复位电流脉冲宽度的比率将写入数据的至少一部分写入相变存储器单元 应用于相变存储器单元。

    Semiconductor memory devices and memory systems including the same
    16.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权

    公开(公告)号：US09767920B2

    公开(公告)日：2017-09-19

    申请号：US14798634

    申请日：2015-07-14

    申请人： Young-Il Kim ,  Hoi-ju Chung

    发明人： Young-Il Kim ,  Hoi-ju Chung

    IPC分类号： G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/52 ,  G11C11/401 ,  G11C29/04

    CPC分类号： G11C29/42 ,  G11C11/401 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0411

    摘要： A semiconductor memory device includes a memory cell array, an input/output (I/O) gating circuit, an error decision circuit and an error check and correction (ECC) circuit. The I/O gating circuit reads test pattern data to provide test result data in a test mode and reads a codeword in a normal mode. The error decision circuit determines the correctability of errors in the test result data by a first unit, based on the test pattern data and the test result data and provides a first error kind signal indicating a first determination result, in the test mode. The ECC circuit decodes the codeword including main data and parity data generated based on the main data, determines correctability of errors in the codeword by a second unit and provides a second error kind signal indicating a second determination result, in the normal mode. The main data includes a plurality of unit data.

    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF WRITING DATA IN THE SAME
    18.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF WRITING DATA IN THE SAME 有权
    半导体存储器件，包括其的存储器系统及其数据写入方法

    公开(公告)号：US20140331101A1

    公开(公告)日：2014-11-06

    申请号：US14160614

    申请日：2014-01-22

    申请人： Hoi-ju CHUNG ,  Chul-sung PARK ,  Jae-Wook LEE ,  Jang-Woo RYU ,  Tae-seong JANG ,  Gong-heum HAN

    发明人： Hoi-ju CHUNG ,  Chul-sung PARK ,  Jae-Wook LEE ,  Jang-Woo RYU ,  Tae-seong JANG ,  Gong-heum HAN

    IPC分类号： G06F11/08 ,  G06F11/10

    CPC分类号： G06F11/1056 ,  G06F11/085 ,  G06F11/1008 ,  G11C29/42

    摘要： In one embodiment, the semiconductor device includes a memory array and a control architecture configured to control reading data from and writing data to the memory array. The control architecture is configured to receive data and a codeword location in the memory array, select one or more data units in the received data based on a data mask, read a codeword currently stored at the codeword location in the memory array, error correct the read codeword to generate a corrected read codeword, form a new codeword from the selected data units of the received data and data units in the corrected read codeword that do not correspond to the selected data units, and write the new codeword to the memory array.

    摘要翻译： 在一个实施例中，半导体器件包括存储器阵列和被配置为控制从存储器阵列读取数据和将数据写入存储器阵列的控制架构。 控制架构被配置为在存储器阵列中接收数据和码字位置，基于数据掩码选择所接收数据中的一个或多个数据单元，读取当前存储在存储器阵列中的码字位置处的码字，错误校正 读取码字以产生经校正的读取码字，从所选择的数据单元中选出的数据单元形成一个新的码字，并且将校验后的读取码字中的数据单元与所选择的数据单元不对应，并将新的代码字写入存储器阵列。

    Memory device, systems and devices including a memory device, methods of operating a memory device, and/or methods of operating systems and devices including a memory device
    20.
    发明授权
    Memory device, systems and devices including a memory device, methods of operating a memory device, and/or methods of operating systems and devices including a memory device 有权
    存储设备，包括存储器设备的系统和设备，操作存储设备的方法，和/或操作系统和设备的方法，包括存储设备

    公开(公告)号：US08531884B2

    公开(公告)日：2013-09-10

    申请号：US13094382

    申请日：2011-04-26

    申请人： Byung Jun Min ,  Hoi Ju Chung

    发明人： Byung Jun Min ,  Hoi Ju Chung

    IPC分类号： G11C11/34

    CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2013/0088 ,  G11C2213/71

    摘要： In one embodiment, a memory device includes a plurality of unit cell arrays. Each unit cell array includes an array of memory cells arranged in a plurality of columns, and each column is associated with a bit line. The memory device further includes a program control circuit configured to program cells in the plurality of unit cell arrays based on program bits associated with the plurality of unit cell arrays. For example, the program control unit is configured to simultaneously program one memory cell in each unit cell array having at least one associated program bit.

    摘要翻译： 在一个实施例中，存储器件包括多个单元阵列。 每个单元阵列包括布置在多个列中的存储单元的阵列，并且每列与位线相关联。 存储装置还包括程序控制电路，其被配置为基于与多个单元阵列相关联的程序位对多个单元阵列中的单元进行编程。 例如，程序控制单元被配置为同时对具有至少一个关联程序位的每个单位单元阵列中的一个存储单元进行编程。