公开(公告)号：US20050126586A1

公开(公告)日：2005-06-16

申请号：US10999183

申请日：2004-11-30

申请人： In-su Ha ,  Yoon-bon Koo ,  Hyun-seok Lim ,  Cheon-su Han ,  Seung-cheol Choi

发明人： In-su Ha ,  Yoon-bon Koo ,  Hyun-seok Lim ,  Cheon-su Han ,  Seung-cheol Choi

IPC分类号： B08B5/00 ,  B08B7/00 ,  C03C23/00 ,  C23C16/44 ,  C23G1/00 ,  H01L21/304 ,  H01L21/3205 ,  H01L21/44

CPC分类号： C23C16/4405 ,  B08B7/00 ,  Y10S438/905

摘要： A semiconductor device fabrication apparatus is cleaned after a conductive layer is formed on a metal oxide layer of a substrate. The substrate is disposed on a heater in a process chamber of the apparatus, and the conductive layer is formed by introducing source gases into the chamber. Then the substrate is transferred out of the process chamber. At least one by-product of a reaction between the source gases and the metal oxide layer adheres to a surface inside the chamber, such as to a region or regions of the heater. Once the semiconductor substrate has been transferred outside the process chamber of the semiconductor fabrication apparatus, the by-product(s) is/are removed by evaporation. The by-product(s) can be evaporated using gas, such as one of the source gases, so that the process chamber can remain closed.

摘要翻译： 在将导电层形成在基板的金属氧化物层上之后，对半导体器件的制造装置进行清洗。 衬底设置在设备的处理室中的加热器上，并且通过将源气体引入室中而形成导电层。 然后将基板转移出处理室。 源气体和金属氧化物层之间的反应的至少一个副产物附着到室内的表面，例如加热器的区域或区域。 一旦半导体衬底已被转移到半导体制造设备的处理室之外，副产物通过蒸发除去。 可以使用诸如源气体之一的气体蒸发副产物，使得处理室保持关闭。

公开(公告)号：US06358829B2

公开(公告)日：2002-03-19

申请号：US09397616

申请日：1999-09-16

申请人： Mee-Young Yoon ,  Sang-In Lee ,  Hyun-Seok Lim

发明人： Mee-Young Yoon ,  Sang-In Lee ,  Hyun-Seok Lim

IPC分类号： H01L2144

CPC分类号： H01L21/76876 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76877

摘要： A method for fabricating a semiconductor device having an aluminum (Al) interconnection layer with excellent surface morphology forms an interface control layer having a plurality of atomic layers before forming the Al interconnection layer. In the fabrication method, an interlayer dielectric (ILD) film having a contact hole which exposes a conductive region of the semiconductor substrate is formed on a semiconductor substrate, and an interface control layer having a plurality of atomic layers continuously deposited is formed on the inner wall of the contact hole and the upper surface of the interlayer dielectric film, to a thickness on the order of several angstroms to several tens of angstroms. Then, chemical vapor deposition (CVD) completes an Al blanket deposition on the resultant structure, including the interface control layer, to form a contact plug in the contact hole and an interconnection layer on the interlayer dielectric film.

摘要翻译： 具有优异表面形态的具有铝（Al）互连层的半导体器件的制造方法在形成Al互连层之前形成具有多个原子层的界面控制层。 在制造方法中，在半导体衬底上形成具有暴露半导体衬底的导电区域的接触孔的层间电介质（ILD）膜，并且在内部形成具有连续沉积的多个原子层的界面控制层 接触孔的壁和层间电介质膜的上表面的厚度达到几埃到几十埃的数量级。 然后，化学气相沉积（CVD）在所得结构（包括界面控制层）上完成Al覆盖层沉积，以形成接触孔中的接触塞和层间电介质膜上的互连层。

公开(公告)号：US10074560B2

公开(公告)日：2018-09-11

申请号：US15601045

申请日：2017-05-22

申请人： Ki-hyun Yoon ,  Hauk Han ,  Yeon-sil Sohn ,  Seul-gi Bae ,  Hyun-seok Lim

发明人： Ki-hyun Yoon ,  Hauk Han ,  Yeon-sil Sohn ,  Seul-gi Bae ,  Hyun-seok Lim

IPC分类号： H01L21/768 ,  H01L21/28 ,  H01L29/40 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11578 ,  H01L29/792 ,  H01L21/822 ,  H01L27/11568 ,  H01L21/8239 ,  H01L27/105 ,  H01L27/11551

CPC分类号： H01L21/76841 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/8221 ,  H01L21/8239 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/66477 ,  H01L29/78642 ,  H01L29/792 ,  H01L29/7926

摘要： A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.

公开(公告)号：US10026746B2

公开(公告)日：2018-07-17

申请号：US15604028

申请日：2017-05-24

申请人： Jeong Gil Lee ,  Jee Yong Kim ,  Jung Hwan Lee ,  Dae Seok Byeon ,  Hyun Seok Lim

发明人： Jeong Gil Lee ,  Jee Yong Kim ,  Jung Hwan Lee ,  Dae Seok Byeon ,  Hyun Seok Lim

IPC分类号： H01L27/115 ,  H01L27/1157 ,  H01L27/11524 ,  H01L23/535 ,  H01L29/06 ,  H01L29/788 ,  H01L29/792 ,  H01L29/423 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

摘要： A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

公开(公告)号：US20180114722A1

公开(公告)日：2018-04-26

申请号：US15464532

申请日：2017-03-21

申请人： Kwang Chul PARK ,  Ji Woon Im ,  Dai Hong Kim ,  ll Woo Kim ,  Hyun Seok Lim

发明人： Kwang Chul PARK ,  Ji Woon Im ,  Dai Hong Kim ,  ll Woo Kim ,  Hyun Seok Lim

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11582 ,  C23C16/48 ,  C23C16/50 ,  C23C16/54

CPC分类号： H01L21/76825 ,  C23C16/45523 ,  C23C16/482 ,  C23C16/50 ,  C23C16/54 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02348 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1157 ,  H01L27/11582

摘要： A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.

公开(公告)号：US20180090325A1

公开(公告)日：2018-03-29

申请号：US15601045

申请日：2017-05-22

申请人： Ki-hyun YOON ,  Hauk HAN ,  Yeon-sil SOHN ,  Seul-gi BAE ,  Hyun-seok LIM

发明人： Ki-hyun YOON ,  Hauk HAN ,  Yeon-sil SOHN ,  Seul-gi BAE ,  Hyun-seok LIM

IPC分类号： H01L21/28 ,  H01L29/40 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11582

CPC分类号： H01L21/76841 ,  H01L21/28088 ,  H01L21/8221 ,  H01L21/8239 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/401 ,  H01L29/66477 ,  H01L29/792 ,  H01L29/7926

摘要： A method of manufacturing a semiconductor device includes forming an insulating pattern layer on a substrate, conformally forming a first conductive layer with a first thickness on the insulating pattern layer, wet etching the first conductive layer to have a second thickness that is less than the first thickness, and forming a second conductive layer on the first conductive layer after wet etching the first conductive layer. The second conductive layer includes a material that is different from a material included in the first conductive layer.

公开(公告)号：US09865617B2

公开(公告)日：2018-01-09

申请号：US15402272

申请日：2017-01-10

申请人： Hauk Han ,  Ji Woon Im ,  Do Hyung Kim ,  Hyun Seok Lim

发明人： Hauk Han ,  Ji Woon Im ,  Do Hyung Kim ,  Hyun Seok Lim

IPC分类号： H01L23/528 ,  H01L29/36 ,  H01L27/11582 ,  H01L29/06 ,  H01L23/522 ,  H01L21/306

CPC分类号： H01L27/11582 ,  H01L21/30604 ,  H01L21/3115 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/36

摘要： A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.

公开(公告)号：US20170330893A1

公开(公告)日：2017-11-16

申请号：US15402272

申请日：2017-01-10

申请人： HAUK HAN ,  JI WOON IM ,  DO HYUNG KIM ,  HYUN SEOK LIM

发明人： HAUK HAN ,  JI WOON IM ,  DO HYUNG KIM ,  HYUN SEOK LIM

IPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L21/306 ,  H01L23/522 ,  H01L29/36 ,  H01L29/06

CPC分类号： H01L27/11582 ,  H01L21/30604 ,  H01L21/3115 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/36

摘要： A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.

公开(公告)号：US20120004476A1

公开(公告)日：2012-01-05

申请号：US13146853

申请日：2010-01-29

申请人： Sung Cheol Yoon ,  So Youn Nam ,  Hyun Seok Lim ,  Jaemin Lee ,  Jongsun Lim ,  Dong Wook Kim ,  Yongku Kang ,  Chang Jin Lee ,  Jae Wook Jung

发明人： Sung Cheol Yoon ,  So Youn Nam ,  Hyun Seok Lim ,  Jaemin Lee ,  Jongsun Lim ,  Dong Wook Kim ,  Yongku Kang ,  Chang Jin Lee ,  Jae Wook Jung

IPC分类号： C07C13/62

CPC分类号： C07C13/48 ,  B82Y10/00 ,  C07C13/58 ,  C07C13/60 ,  C07C2602/10 ,  C07C2603/24 ,  C07C2603/26 ,  H01L51/0047 ,  H01L51/42 ,  Y02E10/549

摘要： The present invention relates to fullerene derivatives and an organic electronic device using the same, and more specifically, to a novel fullerene derivative incorporating an aromatic fused ring compound and to an organic electronic device with excellent electrical properties by employing the fullerene derivative. In more detail, the novel fullerene derivative incorporating an aromatic fused ring compound according to the present invention exhibits excellent solubility in organic solvents and has a high electrochemical electron mobility and a high LUMO energy level, thereby making the fullerene derivative a suitable material for organic solar cells featuring a high open circuit voltage (Voc) and an improved energy conversion efficiency, or applicable for use in organic electronic devices such as organic thin film transistors.

摘要翻译： 本发明涉及富勒烯衍生物和使用该富勒烯衍生物的有机电子器件，更具体地说，涉及一种并入芳族稠合环化合物的新型富勒烯衍生物和通过使用富勒烯衍生物而具有优异电性能的有机电子器件。 更详细地说，掺入本发明芳族稠环化合物的新型富勒烯衍生物在有机溶剂中表现出优异的溶解性，并且具有高电化学电子迁移率和高LUMO能级，从而使富勒烯衍生物成为有机太阳能的合适材料 具有高开路电压（Voc）和提高的能量转换效率的电池，或适用于有机电子器件如有机薄膜晶体管。

公开(公告)号：US07812332B2

公开(公告)日：2010-10-12

申请号：US11769532

申请日：2007-06-27

申请人： Gyu-Hwan Oh ,  In-Sun Park ,  Hyun-Seok Lim ,  Ki-Jong Lee ,  Nak-Hyun Lim

发明人： Gyu-Hwan Oh ,  In-Sun Park ,  Hyun-Seok Lim ,  Ki-Jong Lee ,  Nak-Hyun Lim

IPC分类号： H01L45/00

CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： A phase change memory device includes a current restrictive element interposed between an electrically conductive element and a phase change material. The current restrictive element includes a plurality of overlapping film patterns, each of which having a respective first portion proximal to the conductive element and a second portion proximal to the phase change material. The second portions are configured and dimensioned to have higher resistance than the first portions.

摘要翻译： 相变存储器件包括介于导电元件和相变材料之间的电流限制元件。 电流限制元件包括多个重叠的膜图案，每个重叠的膜图案具有靠近导电元件的相应的第一部分和靠近相变材料的第二部分。 第二部分的构造和尺寸设计成具有比第一部分更高的电阻。