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    Resistive Random Access Memory Devices Including Sidewall Resistive Layers and Related Methods
    13.
    发明申请
    Resistive Random Access Memory Devices Including Sidewall Resistive Layers and Related Methods 审中-公开
    包括侧壁电阻层的电阻随机存取存储器件及相关方法

    公开(公告)号：US20080247219A1

    公开(公告)日：2008-10-09

    申请号：US12062042

    申请日：2008-04-03

    Applicant: Suk-Hun Choi ,  In-Gyu Baek ,  Seong-Kyu Yun ,  Jong-Heun Lim ,  Chagn-Ki Hong ,  Bo-Un Yoon

    Inventor： Suk-Hun Choi ,  In-Gyu Baek ,  Seong-Kyu Yun ,  Jong-Heun Lim ,  Chagn-Ki Hong ,  Bo-Un Yoon

    IPC: G11C11/00 ,  H01C17/00

    CPC classification number: H01L45/04 ,  H01C17/06533 ,  H01L27/2409 ,  H01L27/2472 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1666 ,  Y10T29/49082

    Abstract: A resistive random access memory (RRAM) device may include a first metal pattern on a substrate, a first insulating layer on the first metal pattern and on the substrate, an electrode, a second insulating layer on the first insulating layer, a resistive memory layer, and a second metal pattern. Portions of the first metal pattern may be between the substrate and the first insulating layer, and the first insulating layer may have a first opening therein exposing a portion of the first metal pattern. The electrode may be in the opening with the electrode being electrically coupled with the exposed portion of the first metal pattern. The first insulating layer may be between the second insulating layer and the substrate, and the second insulating layer may have a second opening therein exposing a portion of the electrode. The resistive memory layer may be on side faces of the second opening and on portions of the electrode, and the second metal pattern may be in the second opening with the resistive memory layer between the second metal pattern and the side faces of the second opening and between the second metal pattern and the electrode. Related methods are also discussed.

    Abstract translation: 电阻随机存取存储器（RRAM）器件可以包括衬底上的第一金属图案，第一金属图案上的第一绝缘层和衬底上的第一绝缘层，电极，第一绝缘层上的第二绝缘层，电阻存储层 ，和第二金属图案。 第一金属图案的部分可以在基板和第一绝缘层之间，并且第一绝缘层可以具有其中暴露第一金属图案的一部分的第一开口。 电极可以在开口中，其中电极与第一金属图案的暴露部分电耦合。 第一绝缘层可以在第二绝缘层和衬底之间，并且第二绝缘层可以具有暴露电极的一部分的第二开口。 电阻性存储层可以在第二开口的侧面和电极的部分上，并且第二金属图案可以在第二开口中，第二金属图案和第二开口的侧面之间的电阻性存储层， 在第二金属图案和电极之间。 还讨论了相关方法。

    MAGNETIC TUNNEL JUNCTION STRUCTURE HAVING AN OXIDIZED BUFFER LAYER AND METHOD OF FABRICATING THE SAME
    15.
    发明申请
    MAGNETIC TUNNEL JUNCTION STRUCTURE HAVING AN OXIDIZED BUFFER LAYER AND METHOD OF FABRICATING THE SAME 审中-公开
    具有氧化缓冲层的磁性隧道结结构及其制造方法

    公开(公告)号：US20070041125A1

    公开(公告)日：2007-02-22

    申请号：US11552085

    申请日：2006-10-23

    Applicant: Young-Ki HA ,  Jang-Eun LEE ,  Hyun-Jo KIM ,  Se-Chung OH ,  Jun-Soo BAE ,  In-Gyu BAEK

    Inventor： Young-Ki HA ,  Jang-Eun LEE ,  Hyun-Jo KIM ,  Se-Chung OH ,  Jun-Soo BAE ,  In-Gyu BAEK

    IPC: G11B5/17

    CPC classification number: H01L43/12 ,  H01L43/08

    Abstract: There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.

    Abstract translation: 提供了一种磁性隧道结结构及其制造方法。 磁性隧道结结构包括依次形成在下电极上的下电极，下磁层图案和隧道层图案。 磁隧道结结构还包括依次形成在隧道层图案的一部分上的上磁层图案，缓冲层图案和上电极。 上部磁性层图案的侧壁由氧化的上部磁性层包围，缓冲层图案的侧壁由氧化的缓冲层包围。 可以通过氧化缓冲层来防止磁性隧道结区域中上部磁性层图案和下部磁性层图案的消耗。

    Magneto-resistive memory cells and devices having asymmetrical contacts and methods of fabrication therefor
    17.
    发明申请
    Magneto-resistive memory cells and devices having asymmetrical contacts and methods of fabrication therefor 有权
    具有不对称接触的磁阻存储器单元和器件及其制造方法

    公开(公告)号：US20060215445A1

    公开(公告)日：2006-09-28

    申请号：US11378945

    申请日：2006-03-17

    Applicant: In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

    Inventor： In-Gyu Baek ,  Moon-Sook Lee ,  Dong-Chul Kim

    IPC: G11C11/00

    CPC classification number: H01L45/04 ,  G11C11/161 ,  G11C11/1659 ,  G11C13/0007 ,  G11C2213/52 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

    Abstract: A memory cell includes a plug-type first electrode in a substrate, a magneto-resistive memory element disposed on the first electrode, and a second electrode disposed on the magneto-resistive memory element opposite the first electrode. The second electrode has an area of overlap with the magneto-resistive memory element that is greater than an area of overlap of the first electrode and the magneto-resistive memory element. The first surface may, for example, be substantially circular and have a diameter less than a minimum planar dimension (e.g., width) of the second surface. The magneto-resistive memory element may include a colossal magneto-resistive material, such as an insulating material with a perovskite phase and/or a transition metal oxide.

    Abstract translation: 存储单元包括衬底中的插塞式第一电极，设置在第一电极上的磁阻存储元件，以及设置在与第一电极相对的磁阻存储元件上的第二电极。 第二电极具有与磁阻存储元件重叠的区域，其大于第一电极和磁阻存储元件的重叠区域。 例如，第一表面可以是基本上圆形的并且具有小于第二表面的最小平面尺寸（例如，宽度）的直径。 磁阻存储元件可以包括巨磁阻材料，例如具有钙钛矿相和/或过渡金属氧化物的绝缘材料。

    Magnetic tunnel junction structure having an oxidized buffer layer and method of fabricating the same
    19.
    发明申请
    Magnetic tunnel junction structure having an oxidized buffer layer and method of fabricating the same 有权
    具有氧化缓冲层的磁隧道结结构及其制造方法

    公开(公告)号：US20050035386A1

    公开(公告)日：2005-02-17

    申请号：US10915872

    申请日：2004-08-10

    Applicant: Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Jun-Soo Bae ,  In-Gyu Baek

    Inventor： Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Se-Chung Oh ,  Jun-Soo Bae ,  In-Gyu Baek

    IPC: G11C11/15 ,  H01L21/00 ,  H01L43/08 ,  H01L43/12

    CPC classification number: H01L43/12 ,  H01L43/08

    Abstract: There are provided a magnetic tunnel junction structure and a method of fabricating the same. The magnetic tunnel junction structure includes a lower electrode, a lower magnetic layer pattern and a tunnel layer pattern, which are sequentially formed on the lower electrode. The magnetic tunnel junction structure further includes an upper magnetic layer pattern, a buffer layer pattern, and an upper electrode, which are sequentially formed on a portion of the tunnel layer pattern. The sidewall of the upper magnetic layer pattern is surrounded by an oxidized upper magnetic layer, and the sidewall of the buffer layer pattern is surrounded by an oxidized buffer layer. The depletion of the upper magnetic layer pattern and the lower magnetic layer pattern in the magnetic tunnel junction region can be prevented by the oxidized buffer layer.

    Abstract translation: 提供了一种磁性隧道结结构及其制造方法。 磁性隧道结结构包括依次形成在下电极上的下电极，下磁层图案和隧道层图案。 磁隧道结结构还包括依次形成在隧道层图案的一部分上的上磁层图案，缓冲层图案和上电极。 上部磁性层图案的侧壁由氧化的上部磁性层包围，缓冲层图案的侧壁由氧化的缓冲层包围。 可以通过氧化缓冲层来防止磁性隧道结区域中上部磁性层图案和下部磁性层图案的消耗。

    SEMICONDUCTOR DEVICE
    20.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130037774A1

    公开(公告)日：2013-02-14

    申请号：US13565830

    申请日：2012-08-03

    Applicant: SEONG-HO SONG ,  CHAN-JIN PARK ,  IN-GYU BAEK

    Inventor： SEONG-HO SONG ,  CHAN-JIN PARK ,  IN-GYU BAEK

    IPC: H01L23/48 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

    Abstract: A semiconductor device includes a first horizontal molding pattern, a horizontal electrode pattern disposed on the first horizontal molding pattern, and a second horizontal molding pattern disposed on the horizontal electrode pattern. A vertical structure extends through the horizontal patterns. The vertical structure includes a vertical electrode pattern, a data storage pattern interposed between the vertical electrode pattern and the horizontal patterns, a first buffer pattern interposed between the data storage pattern and the first molding pattern, and a second buffer pattern interposed between the data storage pattern and the second molding pattern and spaced apart from the first buffer pattern.

    Abstract translation: 半导体器件包括第一水平成型图案，设置在第一水平成型图案上的水平电极图案和设置在水平电极图案上的第二水平成型图案。 垂直结构延伸穿过水平图案。 垂直结构包括垂直电极图案，插入在垂直电极图案和水平图案之间的数据存储图案，插入在数据存储图案和第一模制图案之间的第一缓冲图案和插入在数据存储器之间的第二缓冲图案 图案和第二模制图案并且与第一缓冲图案间隔开。

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