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39 条记录 (耗时 0.022 秒)

    Focus detecting system
    12.
    发明授权
    Focus detecting system 失效
    聚焦检测系统

    公开(公告)号：US4974008A

    公开(公告)日：1990-11-27

    申请号：US503090

    申请日：1990-03-30

    申请人： Toshiki Nakayama ,  Junichi Nakamura ,  Masafumi Yamazaki

    发明人： Toshiki Nakayama ,  Junichi Nakamura ,  Masafumi Yamazaki

    IPC分类号： G02B7/36

    CPC分类号： G02B7/36

    摘要： A focus detecting system is provided with a non-destructive type photoelectric conversion element array, an A/D converter for converting the analog output of the photoelectric conversion element array into a corresponding digital value, and a focus-detecting arithmetic circuit for performing arithmetic operations upon the distance to an object on the basis of the digital value output from the A/D converter. In the focus detecting system, when a predetermined initial integration period elapses after the storage of the electric charge has been started, a sequence of in-focus-state detecting operations comprising the steps of effecting non-destructive readout of the output of the photoelectric conversion element array, performing A/D conversion of the readout output and performing arithmetic operations for focus detection is repeatedly executed so that focus detection is effected. With this arrangement, the integration period required for a focus detecting operation can be rationally made as short as possible in accordance with the states of an object, such as brightness and contrast.

    摘要翻译： 焦点检测系统设置有非破坏性光电转换元件阵列，用于将光电转换元件阵列的模拟输出转换为相应数字值的A / D转换器，以及用于执行算术运算的聚焦检测运算电路 基于从A / D转换器输出的数字值到物体的距离。 在焦点检测系统中，当在开始存储电荷之后经过预定的初始积分周期时，一系列对焦状态检测操作包括以下步骤：对光电转换的输出进行非破坏性读出 元件阵列，重复执行读出输出的A / D转换和执行用于焦点检测的算术运算，从而实现焦点检测。 通过这种布置，可以根据诸如亮度和对比度的对象的状态，合理地使焦点检测操作所需的积分周期尽可能短。

    Fuel supply system for an injection-type internal combustion engine
    14.
    发明授权
    Fuel supply system for an injection-type internal combustion engine 失效
    注射型内燃机的燃油供应系统

    公开(公告)号：US4404944A

    公开(公告)日：1983-09-20

    申请号：US290078

    申请日：1981-08-04

    申请人： Masafumi Yamazaki ,  Mikio Suzuki

    发明人： Masafumi Yamazaki ,  Mikio Suzuki

    IPC分类号： F02D19/08 ,  F02D41/00 ,  F02M37/20 ,  F02M69/18 ,  F02D5/02 ,  F02M51/00

    CPC分类号： F02D41/065 ,  F02D19/0605 ,  F02D19/0628 ,  F02D19/0678 ,  F02D19/084 ,  F02D19/087 ,  F02D41/0025 ,  F02M37/20 ,  F02M69/18 ,  F02D2200/0606 ,  F02D2200/0611 ,  F02D2250/02 ,  Y02T10/36

    摘要： A fuel supply system for an injection-type internal combustion engine using a gasoline or alcohol blended gasoline as a fuel. In addition to a conventional fuel supply system there is provided a fuel temperature detector which detects and signals the fuel temperature increases and exceeds a predetermined value and a fuel pressure regulating means responsive to the fuel temperature detector for raising the fuel pressure within the fuel supply line applied to each fuel injector above a constant value regulated according to the pressure difference between the fuel pressure within the fuel supply line and the intake manifold vacuum pressure so as to prevent the fuel supply line from being clogged due to the occurrence of vapor lock at the time when the engine is started at a high fuel temperature or when the engine runs at a low speed under a high fuel temperature.

    摘要翻译： 一种使用汽油或醇混合汽油作为燃料的注射型内燃机的燃料供给系统。 除了传统的燃料供应系统之外，还提供了一种燃料温度检测器，其检测燃料温度升高并超过预定值，并且响应于燃料温度检测器提高燃料供应管线内的燃料压力，燃料压力调节装置 施加到每个燃料喷射器高于根据燃料供应管线内的燃料压力和进气歧管真空压力之间的压力差调节的恒定值，以防止燃料供应管线由于在 发动机在高燃料温度下起动或发动机在高燃料温度下以低速运转时的时间。

    Midpoint potential generating circuit for use in a semiconductor device
    17.
    发明申请
    Midpoint potential generating circuit for use in a semiconductor device 有权

    公开(公告)号：US20070216473A1

    公开(公告)日：2007-09-20

    申请号：US11802454

    申请日：2007-05-23

    申请人： Masafumi Yamazaki ,  Atsushi Takeuchi

    发明人： Masafumi Yamazaki ,  Atsushi Takeuchi

    IPC分类号： G05F1/10

    CPC分类号： G11C5/147

    摘要： An object of the invention is to improve a defect caused at the time of starting a midpoint potential generating circuit for use in a semiconductor device. A bias generating circuit supplies a grounding potential as a bias voltage Vbias and sets a midpoint potential of capacitors C1 and C2 to a grounding potential when a supply voltage VDD is lower than a first reference voltage. When the supply voltage VDD is equal to or higher than the first reference voltage, the bias generating circuit supplies the supply voltage VDD as the bias voltage Vbias. When the bias voltage Vbias is equal to or higher than a second reference voltage, the bias generating circuit supplies a voltage obtained by dividing the supply voltage VPP of the booster power supply circuit as the bias voltage Vbias to a node of the capacitors C1 and C2.

    Semiconductor device
    18.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07243274B2

    公开(公告)日：2007-07-10

    申请号：US11206170

    申请日：2005-08-18

    申请人： Masafumi Yamazaki ,  Takaaki Suzuki ,  Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo ,  Ayako Sato ,  Takayuki Yoneda ,  Noriko Kawamura

    发明人： Masafumi Yamazaki ,  Takaaki Suzuki ,  Toshikazu Nakamura ,  Satoshi Eto ,  Toshiya Miyo ,  Ayako Sato ,  Takayuki Yoneda ,  Noriko Kawamura

    IPC分类号： G11C29/00

    CPC分类号： G11C29/48 ,  G11C29/36

    摘要： An external terminal receives an external signal so as to access the first and second memory chips. The test starting terminal receives a test starting signal activated when the first or second memory chip is tested and inactivated when the first and second memory chips are normally operated. The access signal generator converts the external signal to a memory access signal of the first memory chip. The first selector selects the external signal, which is a test signal, during activation of the test starting signal, selects the memory access signal during the inactivation of the test starting signal. That is, during the test modes, the first memory chip can be directly accessed from the exterior. For this reason, the test program for testing the first memory chip alone can be diverted as the test program following an assembly of the semiconductor device.

    摘要翻译： 外部终端接收外部信号以访问第一和第二存储器芯片。 当第一和第二存储器芯片正常工作时，测试启动终端接收到测试启动信号，当第一或第二存储器芯片被测试和非激活时激活。 访问信号发生器将外部信号转换为第一存储器芯片的存储器访问信号。 第一选择器在激活测试启动信号期间选择作为测试信号的外部信号，在测试启动信号失效期间选择存储器访问信号。 也就是说，在测试模式期间，可以从外部直接访问第一存储器芯片。 因此，在半导体器件的组装之后，用于单独测试第一存储器芯片的测试程序可以作为测试程序转移。

    Semiconductor integrated circuit device
    20.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20050201186A1

    公开(公告)日：2005-09-15

    申请号：US11104501

    申请日：2005-04-13

    申请人： Masafumi Yamazaki ,  Toshiya Uchida

    发明人： Masafumi Yamazaki ,  Toshiya Uchida

    IPC分类号： G11C8/00 ,  G11C11/4074 ,  G11C11/408 ,  H02M3/07

    CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C5/145 ,  G11C8/08 ,  G11C11/4072 ,  G11C11/4085 ,  H02M3/07 ,  H02M2001/009

    摘要： A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.

    摘要翻译： 半导体集成电路装置具有产生升压电压的升压电源电路，利用升压电压驱动的内部电路，以及通过接收升压电压来控制内部电路的控制电路。 升压电源电路具有用于内部电路的第一输出端子和用于控制电路的第二输出端子。 不管从第一端子输出的升压电压的变化如何，来自第二端子的升压电压都具有指定电平。