公开(公告)号：US20100135064A1

公开(公告)日：2010-06-03

申请号：US12533581

申请日：2009-07-31

申请人： Min-Sang Kim ,  Ji-Myoung Lee ,  Hyun-Jun Bae ,  Dong-Won Kim ,  Jun Seo ,  Yong-Hyun Kwon ,  Weon-Wi Jang ,  Keun-Hwi Cho

发明人： Min-Sang Kim ,  Ji-Myoung Lee ,  Hyun-Jun Bae ,  Dong-Won Kim ,  Jun Seo ,  Yong-Hyun Kwon ,  Weon-Wi Jang ,  Keun-Hwi Cho

IPC分类号： G11C11/24 ,  H01L27/108

CPC分类号： H01L27/101 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897 ,  H01L28/40 ,  H01L29/685

摘要： A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.

摘要翻译： 存储器件包括存储单元，其包括存储节点，第一电极和第二电极，所述存储节点存储电荷，并且当所述第二电极通电时，所述第一电极移动以连接到所述存储节点。

公开(公告)号：US20100129976A1

公开(公告)日：2010-05-27

申请号：US12693783

申请日：2010-01-26

申请人： Eun Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim

发明人： Eun Jung Yun ,  Sung-Young Lee ,  Min-Sang Kim ,  Sung-Min Kim

IPC分类号： H01L21/02

CPC分类号： H01L27/10 ,  G11C23/00

摘要： Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern. Related methods are also provided.

摘要翻译： 提供了包括具有包括绝缘特性的上表面的半导体衬底的机电非易失性存储器件。 第一电极图案设置在半导体衬底上。 第一电极图案暴露半导体衬底的表面的部分通过其中。 在第一电极图案和半导体衬底的暴露表面上提供保形位线。 位线与第一电极图案的侧壁间隔开，并且包括具有由电压差产生的弹性的导电材料。 绝缘层图案设置在位于半导体衬底上的位线的上表面上。 第二电极图案与位线间隔开并设置在绝缘层图案上。 第二电极图案面向第一电极图案。 还提供了相关方法。

公开(公告)号：US20090072297A1

公开(公告)日：2009-03-19

申请号：US12154474

申请日：2008-05-23

申请人： Ji-Myoung Lee ,  Min-Sang Kim ,  Eun-Jung Yun ,  Sung-Young Lee ,  In-Hyuk Choi

发明人： Ji-Myoung Lee ,  Min-Sang Kim ,  Eun-Jung Yun ,  Sung-Young Lee ,  In-Hyuk Choi

IPC分类号： H01L21/28 ,  H01L29/792

CPC分类号： H01L27/10 ,  B82Y10/00 ,  G11C11/56 ,  G11C13/025 ,  G11C23/00

摘要： A memory device comprises a cantilever electrode comprising a first portion that is supported by a pad electrode, and that extends from the pad electrode, and further comprising a second portion that arches over an upper part of the lower word line, wherein a lower void is between the second portion of the cantilever electrode and the lower word line, and wherein the second portion of the cantilever electrode, in a first position, is curved, wherein a trap site extends above the cantilever electrode, the trap site separated from the cantilever electrode by an upper void, and wherein an upper word line on the trap site receives a charge that enables the second portion of the cantilever electrode, in a second position, to be curved toward the trap site.

摘要翻译： 存储器件包括悬臂电极，其包括由焊盘电极支撑的第一部分，并且从焊盘电极延伸的第一部分，还包括在下部字线的上部上拱起的第二部分，其中下部空隙为 在所述悬臂电极的第二部分和所述下字线之间，并且其中所述悬臂电极的第二部分处于第一位置是弯曲的，其中捕获位置在所述悬臂电极上方延伸，所述捕获部位与所述悬臂电极分离 通过上部空隙，并且其中陷阱位置处的上部字线接收电荷，使得悬臂电极的第二部分在第二位置能够朝向陷阱位置弯曲。

公开(公告)号：US20090072296A1

公开(公告)日：2009-03-19

申请号：US12154449

申请日：2008-05-23

申请人： Ji-Myoung Lee ,  Min-Sang Kim ,  Eun-Jung Yun ,  Sung-Young Lee ,  In-Hyuk Choi

发明人： Ji-Myoung Lee ,  Min-Sang Kim ,  Eun-Jung Yun ,  Sung-Young Lee ,  In-Hyuk Choi

IPC分类号： H01L21/28 ,  H01L29/792

CPC分类号： H01L27/10 ,  B82Y10/00 ,  G11C11/56 ,  G11C13/025 ,  G11C23/00

摘要： A multibit electro-mechanical memory device capable of increasing an integrated level of memory devices, and a method of manufacturing the same, are provided. The memory device includes a substrate, a bit line in a first direction on the substrate, a lower word line insulated from the bit line and in a second direction intersecting the first direction, a pad electrode isolated from a sidewall of the lower word line and connected to the bit line, a cantilever electrode expending in the first direction over the lower word line with a lower void therebetween, and connected to the pad electrode and curved in a third direction vertical to the first and second direction by an electrical field induced by a charge applied to the lower word line, a trap site expending in the second direction over the cantilever electrode with an upper void therebetween, and an upper word line to which a charge to curve the cantilever electrode in a direction of the trap site is applied, the upper word line on the trap site.

摘要翻译： 提供了能够提高存储器件集成度的多位机电存储器件及其制造方法。 存储器件包括衬底，衬底上的第一方向上的位线，与位线绝缘的下字线和与第一方向相交的第二方向，与下字线的侧壁隔离的焊盘电极，以及 连接到所述位线，悬臂电极沿着所述下字线在所述下字线上延伸，在其间具有较低的空隙，并且连接到所述焊盘电极，并且在垂直于所述第一和第二方向的第三方向上通过由 施加到下字线的电荷，在第二方向上延伸的悬臂电极上的上部空隙的陷阱位置，以及施加沿着陷阱位置的方向弯曲悬臂电极的电荷的上字线 ，陷阱站点上的上位字线。

公开(公告)号：US20080145989A1

公开(公告)日：2008-06-19

申请号：US12040636

申请日：2008-02-29

申请人： Chang-Woo OH ,  Dong-Gun PARK ,  Jeong-Dong CHOE ,  Min-Sang KIM ,  Sung-Min KIM

发明人： Chang-Woo OH ,  Dong-Gun PARK ,  Jeong-Dong CHOE ,  Min-Sang KIM ,  Sung-Min KIM

IPC分类号： H01L29/06

CPC分类号： H01L21/823481 ,  H01L21/76283 ,  H01L29/1079 ,  H01L29/78

摘要： Embodiments of the invention include a partially insulated field effect transistor and a method of fabricating the same. According to some embodiments, a semiconductor substrate is formed by sequentially stacking a bottom semiconductor layer, a sacrificial layer, and a top semiconductor layer. The sacrificial layer may be removed to form a buried gap region between the bottom semiconductor layer and the top semiconductor layer. Then, a transistor may be formed on the semiconductor substrate. The sacrificial layer may be a crystalline semiconductor formed by an epitaxial growth technology.

摘要翻译： 本发明的实施例包括部分绝缘的场效应晶体管及其制造方法。 根据一些实施例，通过顺序堆叠底部半导体层，牺牲层和顶部半导体层来形成半导体衬底。 可以去除牺牲层以在底部半导体层和顶部半导体层之间形成掩埋间隙区域。 然后，可以在半导体衬底上形成晶体管。 牺牲层可以是通过外延生长技术形成的晶体半导体。

公开(公告)号：US20080142904A1

公开(公告)日：2008-06-19

申请号：US12072440

申请日：2008-02-26

申请人： Ming Li ,  Dong-Uk Choi ,  Chang Woo Oh ,  Dong-Won Kim ,  Min-Sang Kim ,  Sung-Hwan Kim ,  Kyoung-Hwan Yeo

发明人： Ming Li ,  Dong-Uk Choi ,  Chang Woo Oh ,  Dong-Won Kim ,  Min-Sang Kim ,  Sung-Hwan Kim ,  Kyoung-Hwan Yeo

IPC分类号： H01L27/108

CPC分类号： H01L29/7883 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/42336 ,  H01L29/42392 ,  H01L29/66825 ,  H01L29/7841

摘要： A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.

公开(公告)号：US20080094895A1

公开(公告)日：2008-04-24

申请号：US11803425

申请日：2007-05-15

申请人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Dong-Gun Park ,  Eun-Jung Yun

发明人： Sung-Young Lee ,  Dong-Won Kim ,  Min-Sang Kim ,  Dong-Gun Park ,  Eun-Jung Yun

IPC分类号： G11C11/34 ,  H01L21/44

CPC分类号： H01L27/101 ,  H01L27/24

摘要： A non-volatile memory device, and method of forming the same, increases or maximizes the performance of an ultramicro-structured device. In one embodiment, a non-volatile memory device comprises a first word line and a second word line insulated from each other and positioned to intersect each other with a vacant space therebetween; a bit line in the vacant space between one of the first word line and the second word line and positioned in parallel with one of the first word line and the second word line, the bit line constructed and arranged to be deflected toward one of the first word line and the second word line by an electric field induced between the first word line and the second word line; and a trap site between the bit line and one of the first word line and the second word line intersecting the bit line, the trap site being insulated from the one of the first word line and the second word line intersecting the bit line and spaced apart from the bit line by a portion of the vacant space, the trap site configured to trap a predetermined electric charge to electrostatically fix the bit line in a deflected position in the direction of the one of the word lines.

摘要翻译： 非易失性存储器件及其形成方法增加或最大化超微结构器件的性能。 在一个实施例中，非易失性存储器件包括第一字线和第二字线，该第一字线和第二字线彼此绝缘并且被定位成彼此相交并具有空隙; 位于第一字线和第二字线中的一个之间的空白空间中的位线，并且与第一字线和第二字线之一平行地定位，位线被构造和布置成朝向第一字线 字线和第二字线由在第一字线和第二字线之间感应的电场; 位线与位线相交的第一字线和第二字线之一之间的陷阱位置，陷阱位置与第一字线和第二字线之一绝缘，与位线相交并间隔开 从位线通过空闲空间的一部分，陷阱位置被配置为捕获预定电荷以将位线静电地固定在一条字线的方向上的偏转位置。

公开(公告)号：US20080093664A1

公开(公告)日：2008-04-24

申请号：US11894449

申请日：2007-08-21

申请人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Dong-Won Kim ,  Sung-Hwan Kim

发明人： Eun-Jung Yun ,  Min-Sang Kim ,  Sung-Min Kim ,  Dong-Won Kim ,  Sung-Hwan Kim

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10876 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42356 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7881 ,  H01L29/7926

摘要： In a memory device and a method of manufacturing the memory device, the memory device includes a first gate electrode enclosed by a first gate insulating layer, a second gate electrode enclosed by a second gate insulating layer that can be an ONO layer, and a channel region vertically extending between the first gate electrode and the second gate electrode. The first gate electrode is used for removing a charge trapped in the second gate insulating layer. Thus, the memory device can have an improved characteristic when performing an erase operation.

摘要翻译： 在存储器件和存储器件的制造方法中，存储器件包括由第一栅极绝缘层包围的第一栅极电极，由可以是ONO层的第二栅极绝缘层包围的第二栅电极，以及通道 在第一栅电极和第二栅电极之间垂直延伸的区域。 第一栅电极用于去除在第二栅极绝缘层中俘获的电荷。 因此，当执行擦除操作时，存储器件可以具有改进的特性。

公开(公告)号：US07332386B2

公开(公告)日：2008-02-19

申请号：US11084922

申请日：2005-03-21

申请人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

发明人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/785 ,  H01L21/26513 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/78624

摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.

摘要翻译： 翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。 翅片在基底上并沿着和垂直方向横向延伸。 栅电极覆盖翅片的一侧和顶部。 栅绝缘层位于栅电极和鳍之间。 翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。 翅片的源极区域具有与鳍片的漏极区域不同的宽度。

公开(公告)号：US20080035928A1

公开(公告)日：2008-02-14

申请号：US11788011

申请日：2007-04-18

申请人： Eunjung Yun ,  Sung-Young Lee ,  Min-sang Kim ,  Sungmin Kim

发明人： Eunjung Yun ,  Sung-Young Lee ,  Min-sang Kim ,  Sungmin Kim

IPC分类号： H01L21/8229 ,  G11C11/34 ,  H01L29/10 ,  H01L21/336

CPC分类号： H01L27/115 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  H01H2059/0045 ,  H01L27/108 ,  H01L27/11568 ,  H01L29/792

摘要： In a memory device and a method of forming a memory device, the device comprises a substrate, a first electrode extending in a vertical direction relative to the substrate, and a second electrode extending in a vertical direction relative to the substrate, the second electrode being spaced apart from the first electrode by a vertical gap. A third electrode is provided that extends in a vertical direction in the electrode gap, the third electrode being spaced apart from the first electrode by a first gap and the third electrode being spaced apart from the second electrode by a second gap, the third electrode being elastically deformable such that the third electrode deflects to be electrically coupled with the first electrode through the first gap in a first bent position and to be electrically coupled with the second electrode through the second gap in a second bent position, and to be isolated from the first electrode and the second electrode in a rest position.

摘要翻译： 在存储器件和形成存储器件的方法中，器件包括衬底，相对于衬底沿垂直方向延伸的第一电极和相对于衬底在垂直方向上延伸的第二电极，第二电极为 与第一电极间隔开垂直间隙。 提供在电极间隙中沿垂直方向延伸的第三电极，第三电极通过第一间隙与第一电极隔开，第三电极通过第二间隙与第二电极间隔开，第三电极为 可弹性变形，使得第三电极在第一弯曲位置偏转通过第一间隙与第一电极电耦合，并且在第二弯曲位置通过第二间隙与第二电极电耦合，并与第一电极隔离 第一电极和第二电极处于静止位置。