公开(公告)号：US12057180B2

公开(公告)日：2024-08-06

申请号：US17934102

申请日：2022-09-21

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Antonino Conte ,  Francois Maugain

IPC: G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  H10B41/30 ,  H10B41/40

CPC classification number: G11C16/3445 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/349 ,  H10B41/30 ,  H10B41/40

Abstract: In an embodiment a non-volatile memory device includes a memory array having a plurality of memory cells, a control unit operatively coupled to the memory array, a biasing stage controllable by the control unit and configured to apply a biasing configuration to the memory cells to perform a memory operation and a reading stage coupled to the memory array and controllable by the control unit, the reading stage configured to verify whether the memory operation has been successful based on a verify level, wherein the control unit is configured to adaptively modify a value of the verify level based on an ageing of the memory cells.

公开(公告)号：US12051656B2

公开(公告)日：2024-07-30

申请号：US18095136

申请日：2023-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Christian Rivero

IPC: H01L23/528 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/8234 ,  H01L23/00 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49

CPC classification number: H01L23/573 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/4916

Abstract: An integrated circuit includes a substrate, an interconnection part, and an isolating region located between the substrate and the interconnection part. A decoy structure is located within the isolating region and includes a silicided sector which is electrically isolated from the substrate.

公开(公告)号：US12038801B2

公开(公告)日：2024-07-16

申请号：US18081011

申请日：2022-12-14

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Sylvain Chavagnat ,  Simon Valcin

IPC: G06F1/3234

CPC classification number: G06F1/3243

Abstract: Disclosed herein is a debug system including a host computer, a microcontroller, and a debug probe for interface therebetween for performing debug trace operations. The debug probe samples the current drawn by the microcontroller. The debug probe and host computer cooperate so as to acquire and accurately align trace data and the samples of the current drawn by the microcontroller. Techniques for performing this alignment are described herein and enable for accurate inferences to be drawn about the current drawn by the microcontroller during different program operations.

公开(公告)号：US12019510B2

公开(公告)日：2024-06-25

申请号：US17684198

申请日：2022-03-01

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Albert Martinez ,  Patrick Haddad

IPC: G06F7/58 ,  G06F11/10 ,  G06F11/26

CPC classification number: G06F11/10 ,  G06F7/58 ,  G06F11/26

Abstract: The present disclosure relates to a circuit for testing a random number generator adapted to delivering a series of random bits and comprising at least one test unit configured to detect a defect in the series of random bits, said test circuit being adapted to verifying whether, after the detection of a first defect by the test unit, the number of random bits, generated by the random number generator without the detection of a second defect by said unit test, is smaller than a first threshold.

公开(公告)号：US20240194679A1

公开(公告)日：2024-06-13

申请号：US18524915

申请日：2023-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe Bienvenu ,  Julia Castellan ,  Antonio Calandra

IPC: H01L27/092 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H02P7/03

CPC classification number: H01L27/0922 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41758 ,  H01L29/7813 ,  H01L29/7816 ,  H02P7/04

Abstract: An integrated monolithic H-bridge is formed in a bulk semiconductor region. A first branch includes a first vertical MOS transistor and a second lateral MOS transistor integrated in the bulk semiconductor region. The first vertical MOS transistor and the second lateral MOS transistor are coupled in series. A second branch includes a third vertical MOS transistor and a fourth lateral MOS transistor integrated in the bulk semiconductor region. The third vertical MOS transistor and the fourth lateral MOS transistor are coupled in series and the first and second branches being coupled in parallel.

公开(公告)号：US20240186318A1

公开(公告)日：2024-06-06

申请号：US18526384

申请日：2023-12-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Joel METZ ,  Brice ARRAZAT

IPC: H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/94

CPC classification number: H01L27/0629 ,  H01L29/42336 ,  H01L29/66181 ,  H01L29/945

Abstract: An integrated circuit includes a capacitive transistor supported by a semiconductor substrate. The capacitive transistor includes: a drain and a source formed in the semiconductor substrate; a gate having a first portion extending in depth in the semiconductor substrate, and a second portion prolonging said first portion and extending over the semiconductor substrate; and a dielectric layer extending between the gate and the semiconductor substrate.

公开(公告)号：US11967900B2

公开(公告)日：2024-04-23

申请号：US17366353

申请日：2021-07-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Sebastien Ortet ,  Olivier Lauzier

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/36

CPC classification number: H02M3/158 ,  H02M1/0032 ,  H02M1/0083 ,  H02M1/36

Abstract: An embodiment voltage converter includes a first transistor connected between a first node of the converter and a second node configured to receive a power supply voltage, a second transistor connected between the first node and a third node configured to receive a reference potential, a first circuit configured to control the first and second transistors, and a comparator including first and second inputs. The first input is configured to receive, during a first phase, a first voltage ramp and, during a second phase, a set point voltage. The second input is configured to receive, during the first phase, the set point voltage and, during the second phase, a second voltage ramp.

公开(公告)号：US11943931B2

公开(公告)日：2024-03-26

申请号：US17220286

申请日：2021-04-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Quentin Hubert ,  Abderrezak Marzaki ,  Julien Delalleau

IPC: H10B43/35 ,  G11C5/06 ,  H10B43/10

CPC classification number: H10B43/35 ,  G11C5/063 ,  H10B43/10

Abstract: In one embodiment, a non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.

公开(公告)号：US20240095502A1

公开(公告)日：2024-03-21

申请号：US18470281

申请日：2023-09-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pierre Demaj ,  Laurent Folliot

IPC: G06N3/0464

CPC classification number: G06N3/0464

Abstract: An artificial neural network includes a unit cell. The unit cell includes a first binary two-dimensional convolution layer configured to receive an input tensor and to generate a first tensor. A first batch normalization layer is configured to receive the first tensor and to generate a second tensor. A concatenation layer is configured to generate a third tensor by concatenating the input tensor and the second tensor. A second binary two-dimensional convolution layer is configured to receive the third tensor and to generate a fourth tensor. A second batch normalization layer is configured to generate an output tensor based on the fourth tensor.

公开(公告)号：US20240081160A1

公开(公告)日：2024-03-07

申请号：US18506383

申请日：2023-11-10

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Simon JEANNOT

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/061 ,  H10N70/253 ,  H10N70/823 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/8828 ,  G11C13/0004

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.