利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

129 条记录 (耗时 0.03 秒)

    MULTILAYER CHIP CAPACITOR
    11.
    发明申请
    MULTILAYER CHIP CAPACITOR 有权
    多层芯片电容器

    公开(公告)号：US20100254070A1

    公开(公告)日：2010-10-07

    申请号：US12817046

    申请日：2010-06-16

    申请人： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

    发明人： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

    IPC分类号： H01G4/228

    CPC分类号： H01G4/30 ,  H01G4/012 ,  H01G4/232

    摘要： A multilayer chip capacitor includes: a capacitor body having first and second side surfaces and a bottom surface; a plurality of first and second internal electrodes in the capacitor body; first and second external electrodes having a first polarity and formed on the first and second side surfaces, respectively, to cover a respective lower edge of the side surfaces and to partially extend to the bottom surface; and a third external electrode having a second polarity and formed on the bottom surface. The internal electrodes are disposed in perpendicular to the bottom surface. Each of the first internal electrodes has a first lead drawn to the first side and bottom surfaces and a second lead drawn to the second side and bottom surfaces. Each of the second internal electrodes has a third lead drawn to the bottom surface.

    摘要翻译： 一种多层片状电容器包括：具有第一和第二侧表面和底表面的电容器本体; 电容器主体中的多个第一和第二内部电极; 第一和第二外部电极分别具有第一极性并形成在第一和第二侧表面上，以覆盖侧表面的相应下边缘并部分地延伸到底面; 和具有第二极性并形成在底面上的第三外部电极。 内部电极垂直于底面设置。 每个第一内部电极具有被引导到第一侧面和底部表面的第一引线和被引导到第二侧面和底部表面的第二引线。 每个第二内部电极具有被引导到底面的第三引线。

    Method for fabricating capacitor in semiconductor device
    12.
    发明申请
    Method for fabricating capacitor in semiconductor device 审中-公开
    在半导体器件中制造电容器的方法

    公开(公告)号：US20100124811A1

    公开(公告)日：2010-05-20

    申请号：US12318505

    申请日：2008-12-30

    申请人： Sang-Soo Park ,  Jung-Taik Cheong

    发明人： Sang-Soo Park ,  Jung-Taik Cheong

    IPC分类号： H01L21/02

    CPC分类号： H01L28/90 ,  H01L28/92

    摘要： A method for fabricating a capacitor in a semiconductor device includes forming a sacrificial layer over a substrate, forming an opening by selectively etching the sacrificial layer, forming a conductive layer for a lower electrode over a whole surface of a resultant structure including the opening, forming the lower electrode by performing a first blanket dry etching process on the conductive layer until the sacrificial layer is exposed, etching the sacrificial layer to a predetermined depth to protrude a top of the lower electrode over the sacrificial layer, and performing a second blanket dry etching process on the lower electrode to remove a hornlike part on top of the lower electrode. Since a blanket dry etching is performed twice, it is possible to easily remove a hornlike part of a lower electrode and prevent a device failure induced by a micro-bridge between adjacent lower electrodes.

    摘要翻译： 一种在半导体器件中制造电容器的方法包括在衬底上形成牺牲层，通过选择性蚀刻牺牲层形成开口，在包括开口的成形结构的整个表面上形成用于下电极的导电层，形成 所述下电极通过在所述导电层上进行第一覆盖干蚀刻工艺直到所述牺牲层被暴露，将所述牺牲层蚀刻到预定深度以在所述牺牲层上方突出所述下电极的顶部，以及执行第二覆盖干蚀刻 在下电极上去除下电极顶部的角状部分。 由于进行二次干法蚀刻，因此可以容易地除去下部电极的角状部分，并且防止由相邻的下部电极之间的微型桥引起的器件故障。

    ORGANIC ELECTROLUMINESCENCE DISPLAY INCLUDING A SPACER AND METHOD FOR FABRICATING THE SAME
    13.
    发明申请
    ORGANIC ELECTROLUMINESCENCE DISPLAY INCLUDING A SPACER AND METHOD FOR FABRICATING THE SAME 有权
    包括间隔物的有机电致发光显示器及其制造方法

    公开(公告)号：US20100033084A1

    公开(公告)日：2010-02-11

    申请号：US12489167

    申请日：2009-06-22

    申请人： Jung-Woo KO ,  Sang-Shin LEE ,  Sang-Soo PARK ,  Taek-Kyo KANG ,  Seung-Ju HONG

    发明人： Jung-Woo KO ,  Sang-Shin LEE ,  Sang-Soo PARK ,  Taek-Kyo KANG ,  Seung-Ju HONG

    IPC分类号： H01J1/54 ,  H01J9/20

    CPC分类号： H01L27/3246 ,  H01L51/5012

    摘要： Embodiments of the present disclosure provide an organic electroluminescence display device. The display device may include a set of multi-directional spacers that are interposed between the pixels of the display. In one embodiment, the spacers are positioned in both lengthwise and crosswise directions. In another embodiment, the spacers include a first portion that is extends lengthwise between pixels and one or more portions that extend laterally from the first portion between pixels. In yet another embodiment, the spacers include portions that extend in multiple directions between pixels. The spacers may substantially surround each of the pixels and may serve as a boundary, for example, that prevents organic material for one pixel from being incorrectly deposited in another pixel. The spacers can be configured as a support structure, such as, for a metal mask during fabrication of the display device. In addition, the multi-directional aspect of the spacers may be useful in protecting the pixels from damage, such as, when a metal mask is moved during mounting or during fabrication of the display device.

    摘要翻译： 本公开的实施方案提供了一种有机电致发光显示装置。 显示装置可以包括插入在显示器的像素之间的一组多方向​​间隔物。 在一个实施例中，间隔件沿长度方向和横向方向定位。 在另一个实施例中，间隔物包括在像素之间纵向延伸的第一部分和从像素之间的第一部分横向延伸的一个或多个部分。 在另一个实施例中，间隔物包括在像素之间沿多个方向延伸的部分。 间隔件可以基本上围绕每个像素并且可以用作边界，例如，阻止一个像素的有机材料被错误地沉积在另一个像素中。 间隔件可以被配置为支撑结构，例如在显示装置制造期间用于金属掩模。 此外，间隔物的多方面方面可用于保护像素免受损坏，例如当金属掩模在安装期间或在制造显示装置期间移动时。

    Multilayer chip capacitor, circuit board apparatus having the capacitor, and circuit board
    14.
    发明授权
    Multilayer chip capacitor, circuit board apparatus having the capacitor, and circuit board 有权
    多层片式电容器，具有电容器的电路板装置和电路板

    公开(公告)号：US07630208B2

    公开(公告)日：2009-12-08

    申请号：US12198342

    申请日：2008-08-26

    申请人： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

    发明人： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

    IPC分类号： H05K1/16

    CPC分类号： H01G4/232 ,  H01G4/012 ,  H01G4/30 ,  H01G4/385 ,  H05K1/0231 ,  H05K1/113 ,  H05K2201/09309 ,  H05K2201/09772 ,  H05K2201/0979 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611

    摘要： Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.

    摘要翻译： 本发明提供一种多层片状电容器，其包括具有层叠方向配置的第一和第二电容器单元的电容器体; 以及形成在电容器主体外部的多个外部电极。 第一电容器单元包括交替设置在电容器主体的内部的至少一对第一和第二内部电极，第二电容器单元包括交替设置在电容器主体内部的多个第三和第四内部电极， 并且第一至第四内部电极耦合到第一至第四外部电极。 第一电容器单元具有比第二电容器单元更低的等效串联电感（ESL），并且第一电容器单元具有比第二电容器单元更高的等效串联电阻（ESR）。

    Multilayer capacitor array
    17.
    发明申请
    Multilayer capacitor array 有权
    多层电容阵列

    公开(公告)号：US20080158773A1

    公开(公告)日：2008-07-03

    申请号：US11979875

    申请日：2007-11-09

    申请人： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

    发明人： Byoung Hwa Lee ,  Sung Kwon Wi ,  Hae Suk Chung ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

    IPC分类号： H01G4/228 ,  H01G4/005

    CPC分类号： H01G4/232 ,  H01G4/005 ,  H01G4/30 ,  H03H2001/0014

    摘要： A multilayer capacitor array having a plurality of multilayer capacitor devices formed in a single multilayer structure, the multilayer capacitor array including: a capacitor body formed by depositing a plurality of dielectric layers and having first and second side surfaces opposite to each other; a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer there between, and formed of a single electrode plate comprising a single lead, respectively; and a plurality of first polarity external electrodes and second polarity external electrodes, formed on the first side surface and second side surface, respectively, and connected to a correspondent polarity internal electrode via the lead, the first polarity external electrode formed on the first side surface and the second polarity external electrode formed on the second side surface, wherein the numbers of the first polarity external electrodes and the second polarity external electrodes are two or more, respectively, and are identical to each other, and a total number of the multilayer capacitor devices in the multilayer capacitor array is identical to the number of the first polarity external electrodes.

    摘要翻译： 1.一种多层电容器阵列，具有形成为单层多层结构的多层多层电容器件，所述层叠电容器阵列包括：通过沉积多个电介质层而形成的电容器体，并且具有彼此相对的第一和第二侧面; 多个第一极性内部电极和第二极性内部电极，其彼此相对设置在电容器主体中，分别在其间插入电介质层，并由单个引线构成的单个电极板形成; 以及多个第一极性外部电极和第二极性外部电极，分别形成在所述第一侧面和所述第二侧面上，并且经由所述引线与相应的极性内部电极连接，所述第一极性外部电极形成在所述第一侧面 和形成在第二侧面上的第二极性外部电极，其中第一极性外部电极和第二极性外部电极的数量分别为两个或更多个，并且彼此相同，并且层叠电容器的总数 多层电容器阵列中的器件与第一极性外部电极的数量相同。

    Laminated balun transformer
    18.
    发明授权
    Laminated balun transformer 有权
    叠层平衡不平衡变压器

    公开(公告)号：US07183872B2

    公开(公告)日：2007-02-27

    申请号：US11065232

    申请日：2005-02-24

    申请人： Byoung Hwa Lee ,  Dong Seok Park ,  Min Cheol Park ,  Sang Soo Park

    发明人： Byoung Hwa Lee ,  Dong Seok Park ,  Min Cheol Park ,  Sang Soo Park

    IPC分类号： H03H7/42 ,  H01F5/00

    CPC分类号： H01P5/10

    摘要： A laminated balun transformer subminiaturized with a transmission line length reduced below λ/4 without any variation of characteristics. The laminated balun transformer includes a first strip line having one end inputted to a unbalanced signal; a second strip line having connected to the first strip line; a third strip line formed in parallel with the first strip line and connected to a ground and connected to the external electrode for a first balanced signal; a fourth strip line formed in parallel with the second strip line and connected to the external electrode for a ground and the external electrode for a second balanced signal; and a capacitance forming electrode formed in parallel with a portion of the opened end of the second strip line and connected to the external electrode for the unbalanced signal.

    摘要翻译： 传输线长度小于λ/ 4的小型化的不平衡 - 不平衡转换变压器，没有任何特性变化。 叠层平衡不平衡变压器包括：一端输入不平衡信号的第一带状线; 连接到第一带状线的第二带状线; 第三带状线，与第一带状线平行地形成并连接到接地并连接到外部电极用于第一平衡信号; 第四带状线，与第二条带线平行地形成并连接到用于接地的外部电极和用于第二平衡信号的外部电极; 以及电容形成电极，其与所述第二带状线的开放端部的一部分平行地形成，并且与所述不平衡信号的外部电极连接。

    Nonvolatile memory device and read method thereof
    19.
    发明授权
    Nonvolatile memory device and read method thereof 有权

    公开(公告)号：US10090046B2

    公开(公告)日：2018-10-02

    申请号：US15341253

    申请日：2016-11-02

    申请人： Sang-Soo Park ,  June-Hong Park ,  Dongkyo Shim

    发明人： Sang-Soo Park ,  June-Hong Park ,  Dongkyo Shim

    IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/28 ,  G11C16/10 ,  G11C16/08 ,  G11C29/02 ,  G11C29/52

    摘要： Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a cell array including a plurality of memory cells, a page buffer including a plurality of latch sets, and a control logic. The page buffer is connected to the cell array through bit lines. The latch sets respectively are configured to sense data from selected memory cells among the memory cells through the bit lines. The latch sets respectively are configured to perform a plurality of read operations to determine one data state. The latch sets are respectively configured to store results of the read operations. The control logic configured to control the page buffer such that the latch sets sequentially and respectively store the results of the read operations, to compare data stored in the latch sets with each other, and to select one latch set among the latch sets based on the comparison result.

    NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF
    20.
    发明申请
    NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF 审中-公开

    公开(公告)号：US20170133087A1

    公开(公告)日：2017-05-11

    申请号：US15341253

    申请日：2016-11-02

    申请人： Sang-Soo PARK ,  June-Hong PARK ,  Dongkyo SHIM

    发明人： Sang-Soo PARK ,  June-Hong PARK ,  Dongkyo SHIM

    IPC分类号： G11C11/56 ,  G11C16/28 ,  G11C16/08

    CPC分类号： G11C11/5671 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/28 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52

    摘要： Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a cell array including a plurality of memory cells, a page buffer including a plurality of latch sets, and a control logic. The page buffer is connected to the cell array through bit lines. The latch sets respectively are configured to sense data from selected memory cells among the memory cells through the bit lines. The latch sets respectively are configured to perform a plurality of read operations to determine one data state. The latch sets are respectively configured to store results of the read operations. The control logic configured to control the page buffer such that the latch sets sequentially and respectively store the results of the read operations, to compare data stored in the latch sets with each other, and to select one latch set among the latch sets based on the comparison result.