公开(公告)号：US20140248718A1

公开(公告)日：2014-09-04

申请号：US14183257

申请日：2014-02-18

Applicant: Jisoo Kim ,  Mang-mang Ling ,  Khoi Doan ,  Srinivas D. Nemani

Inventor： Jisoo Kim ,  Mang-mang Ling ,  Khoi Doan ,  Srinivas D. Nemani

IPC: H01L43/12

CPC classification number: H01L43/12

Abstract: Chemical modification of non-volatile magnetic random access memory (MRAM) magnetic tunnel junctions (MTJs) for film stack etching is described. In an example, a method of etching a MTJ film stack includes modifying one or more layers of the MTJ film stack with a phosphorous trifluoride (PF3) source to provide modified regions of the MTJ film stack. The modified regions of the MTJ film stack are removed by a plasma etch process.

Abstract translation: 描述了用于薄膜叠层蚀刻的非易失磁性随机存取存储器（MRAM）磁隧道结（MTJ）的化学修饰。 在一个实例中，蚀刻MTJ薄膜叠层的方法包括用三氟化磷（PF 3）源修饰MTJ薄膜叠层的一层或多层以提供MTJ薄膜叠层的修饰区域。 通过等离子体蚀刻工艺去除MTJ薄膜叠层的改性区域。

公开(公告)号：US20140038311A1

公开(公告)日：2014-02-06

申请号：US13750892

申请日：2013-01-25

Applicant: Jisoo Kim ,  Mang-Mang Ling ,  Khoi Doan ,  Chi Hong Ching ,  Srinivas D. Nemani

Inventor： Jisoo Kim ,  Mang-Mang Ling ,  Khoi Doan ,  Chi Hong Ching ,  Srinivas D. Nemani

IPC: H01L43/12

CPC classification number: H01L43/12 ,  G11C11/16 ,  G11C11/161 ,  H01L27/222 ,  H01L43/08

Abstract: Embodiments of the invention provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in magnetoresistive random access memory applications. In one embodiment, a method of forming a MTJ structure on a substrate includes providing a substrate having a insulating tunneling layer disposed between a first and a second ferromagnetic layer disposed on the substrate, wherein the first ferromagnetic layer is disposed on the substrate followed by the insulating tunneling layer and the second ferromagnetic layer sequentially, supplying an ion implantation gas mixture to implant ions into the first ferromagnetic layer exposed by openings defined by the second ferromagnetic layer, and etching the implanted first ferromagnetic layer

Abstract translation: 本发明的实施例提供了用于在磁阻随机存取存储器应用中在衬底上制造磁性隧道结（MTJ）结构的方法和装置。 在一个实施例中，在衬底上形成MTJ结构的方法包括提供衬底，其具有设置在设置在衬底上的第一和第二铁磁层之间的绝缘隧穿层，其中第一铁磁层设置在衬底上， 绝缘隧道层和第二铁磁层，提供离子注入气体混合物以将离子注入到由第二铁磁层限定的开口暴露的第一铁磁层中，并蚀刻所植入的第一铁磁层

公开(公告)号：US08232176B2

公开(公告)日：2012-07-31

申请号：US11765944

申请日：2007-06-20

Applicant: Dmitry Lubomirsky ,  Srinivas D. Nemani ,  Ellie Yieh

Inventor： Dmitry Lubomirsky ,  Srinivas D. Nemani ,  Ellie Yieh

IPC: H01L21/762

CPC classification number: H01L21/76229

Abstract: Methods to reduce film cracking in a dielectric layer are described. The methods may include the steps of depositing a first dielectric film on a substrate and removing a top portion of the first dielectric film by performing an etch on the film. The methods may also include depositing a second dielectric film over the etched first film, and removing a top portion of the second dielectric film. In addition, the methods may include annealing the first and second dielectric films to form the dielectric layer, where the removal of the top portions from the first and the second dielectric films reduces a stress level in the dielectric layer.

Abstract translation: 描述了减少电介质层中的膜破裂的方法。 所述方法可以包括以下步骤：在衬底上沉积第一电介质膜并通过对膜进行蚀刻来去除第一电介质膜的顶部。 所述方法还可以包括在蚀刻的第一膜上沉积第二电介质膜，以及去除第二电介质膜的顶部。 此外，所述方法可以包括退火第一和第二介电膜以形成电介质层，其中从第一和第二电介质膜去除顶部部分降低了介电层中的应力水平。

公开(公告)号：US07902080B2

公开(公告)日：2011-03-08

申请号：US11753968

申请日：2007-05-25

Applicant: Xiaolin Chen ,  Srinivas D. Nemani ,  Shankar Venkataraman

Inventor： Xiaolin Chen ,  Srinivas D. Nemani ,  Shankar Venkataraman

IPC: H01L21/302

CPC classification number: C23C16/045 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31633

Abstract: Methods of filling a gap on a substrate with silicon oxide are described. The methods may include the steps of introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber, reacting the precursors to form a first silicon oxide layer in the gap on the substrate, and etching the first silicon oxide layer to reduce the carbon content in the layer. The methods may also include forming a second silicon oxide layer on the first layer, and etching the second layer to reduce the carbon content in the second layer. The silicon oxide layers are annealed after the gap is filled.

Abstract translation: 描述了用氧化硅填充衬底上的间隙的方法。 所述方法可以包括以下步骤：将有机硅前体和氧前体引入沉积室，使前体反应以在衬底上的间隙中形成第一氧化硅层，并蚀刻第一氧化硅层以还原碳 内容在图层中。 所述方法还可以包括在第一层上形成第二氧化硅层，并蚀刻第二层以降低第二层中的碳含量。 在填充间隙之后对氧化硅层进行退火。

公开(公告)号：US07867923B2

公开(公告)日：2011-01-11

申请号：US11876538

申请日：2007-10-22

Applicant: Abhijit Basu Mallick ,  Srinivas D. Nemani ,  Ellie Yieh

Inventor： Abhijit Basu Mallick ,  Srinivas D. Nemani ,  Ellie Yieh

IPC: H01L21/02

CPC classification number: C23C16/345 ,  C23C16/452 ,  C23C16/56

Abstract: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.

Abstract translation: 一种在衬底上沉积含硅和氮的膜的方法。 该方法包括将含硅前体引入到包含基底的沉积室中，其中含硅前体包含至少两个硅原子。 该方法还包括用位于沉积室外部的远程等离子体系统产生至少一种自由基氮前体。 此外，该方法包括将自由基氮前体引入沉积室，其中自由基含氮和含硅前体将含硅和氮的膜反应并沉积在基底上。 此外，该方法包括在蒸汽环境中退火含硅和氮的膜以形成氧化硅膜，其中蒸汽环境包括水和酸性蒸汽。

公开(公告)号：US07745351B2

公开(公告)日：2010-06-29

申请号：US12252260

申请日：2008-10-15

Applicant: Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

Inventor： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/3105 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612

Abstract: Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate. The substrate is transferred into a chamber suitable for dielectric deposition. A dielectric layer is deposited over the substrate, filling the trench and covering mesa regions adjacent to the trench. The substrate is raised to an elevated position above the substrate support and exposed to a plasma which increases the tensile stress of the substrate. The substrate is removed from the dielectric deposition chamber, and portions of the dielectric layer are removed so that the dielectric layer is even with the topmost portion of the nitride layer. The nitride and pad oxide layers are removed to form the STI structure.

Abstract translation: 描述了通过在升高的位置处的等离子体处理来增加层的拉伸应力的电介质层的形成方法。 在一个实施例中，将氧化物和氮化物层沉积在衬底上并图案化以形成开口。 沟槽被蚀刻到衬底中。 将基底转移到适合于电介质沉积的室中。 介电层沉积在衬底上，填充沟槽并覆盖与沟槽相邻的台面区域。 将衬底升高到衬底支撑件上方的升高位置并暴露于等离子体，这增加了衬底的拉伸应力。 从电介质沉积室取出基板，除去介质层的部分，使得介质层与氮化物层的最上部分均匀。 去除氮化物层和衬垫氧化物层以形成STI结构。

公开(公告)号：US20090208880A1

公开(公告)日：2009-08-20

申请号：US12034000

申请日：2008-02-20

Applicant: SRINIVAS D. NEMANI ,  Shankar Venkataraman ,  Ellie Y. Yieh

Inventor： SRINIVAS D. NEMANI ,  Shankar Venkataraman ,  Ellie Y. Yieh

IPC: G03F7/00 ,  C23F1/00

CPC classification number: G03F7/0757 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31612 ,  H01L21/6719 ,  H01L21/67207

Abstract: Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.

Abstract translation: 根据本发明的一个实施方案公开了使用紫外光图案化硬掩膜的方法和系统。 本发明的实施例减轻了沉积和蚀刻光刻胶的处理问题，以产生硬掩模图案。 首先将诸如氧化硅的硬掩模层沉积在沉积室内的衬底上。 在一些情况下，硬掩模层在沉积之后被烘烤或退火。 之后，硬掩模层的一部分用紫外线照射。 紫外光产生硬掩模材料的暴露和未曝光部分的图案。 曝光后，可能会发生腐蚀过程，例如湿蚀刻，从而去除硬掩模的未曝光部分。 在蚀刻之后，可以对硬掩模进行退火，烘烤或进行等离子体处理。

公开(公告)号：US07498273B2

公开(公告)日：2009-03-03

申请号：US11549930

申请日：2006-10-16

Applicant: Abhijit Basu Mallick ,  Jeffrey C. Munro ,  Srinivas D. Nemani

Inventor： Abhijit Basu Mallick ,  Jeffrey C. Munro ,  Srinivas D. Nemani

IPC: H01L21/00

CPC classification number: C23C16/045 ,  C23C16/401 ,  C23C16/452 ,  C23C16/45525 ,  C23C16/45553 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/3122 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76224 ,  Y10S438/931

Abstract: Methods of depositing a dielectric layer in a gap formed on a substrate are described. The methods include introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber. The organo-silicon precursor has a C:Si atom ratio of less than 8, and the oxygen precursor comprises atomic oxygen that is generated outside the deposition chamber. The precursors are reacted to form the dielectric layer in the gap. Methods of filling gaps with dielectric materials are also described. These methods include providing an organo-silicon precursor having a C:Si atom ratio of less than 8 and an oxygen precursor, and generating a plasma from the precursors to deposit a first portion of the dielectric material in the gap. The dielectric material may be etched, and a second portion of dielectric material may be formed in the gap. The first and second portions of the dielectric material may be annealed.

Abstract translation: 描述了在形成在衬底上的间隙中沉积电介质层的方法。 所述方法包括将有机硅前体和氧前体引入沉积室。 有机硅前体的C：Si原子比小于8，氧前体包括在沉积室外产生的原子氧。 反应前体在间隙中形成电介质层。 还描述了用介电材料填充间隙的方法。 这些方法包括提供C：Si原子比小于8的有机硅前体和氧前体，并从前体产生等离子体以在间隙中沉积介电材料的第一部分。 电介质材料可以被蚀刻，并且介电材料的第二部分可以形成在间隙中。 电介质材料的第一和第二部分可以退火。

公开(公告)号：US20070281495A1

公开(公告)日：2007-12-06

申请号：US11549930

申请日：2006-10-16

Applicant: Abhijit Basu Mallick ,  Jeffrey C. Munro ,  Srinivas D. Nemani

Inventor： Abhijit Basu Mallick ,  Jeffrey C. Munro ,  Srinivas D. Nemani

IPC: H01L21/31

CPC classification number: C23C16/045 ,  C23C16/401 ,  C23C16/452 ,  C23C16/45525 ,  C23C16/45553 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/3122 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76224 ,  Y10S438/931

Abstract: Methods of depositing a dielectric layer in a gap formed on a substrate are described. The methods include introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber. The organo-silicon precursor has a C:Si atom ratio of less than 8, and the oxygen precursor comprises atomic oxygen that is generated outside the deposition chamber. The precursors are reacted to form the dielectric layer in the gap. Methods of filling gaps with dielectric materials are also described. These methods include providing an organo-silicon precursor having a C:Si atom ratio of less than 8 and an oxygen precursor, and generating a plasma from the precursors to deposit a first portion of the dielectric material in the gap. The dielectric material may be etched, and a second portion of dielectric material may be formed in the gap. The first and second portions of the dielectric material may be annealed.

Abstract translation: 描述了在形成在衬底上的间隙中沉积电介质层的方法。 所述方法包括将有机硅前体和氧前体引入沉积室。 有机硅前体的C：Si原子比小于8，氧前体包括在沉积室外产生的原子氧。 反应前体在间隙中形成电介质层。 还描述了用介电材料填充间隙的方法。 这些方法包括提供C：Si原子比小于8的有机硅前体和氧前体，并从前体产生等离子体以在间隙中沉积介电材料的第一部分。 电介质材料可以被蚀刻，并且介电材料的第二部分可以形成在间隙中。 电介质材料的第一和第二部分可以退火。

公开(公告)号：US06897163B2

公开(公告)日：2005-05-24

申请号：US10355379

申请日：2003-01-31

Applicant: Frederic Gaillard ,  Srinivas D. Nemani

Inventor： Frederic Gaillard ,  Srinivas D. Nemani

IPC: C23C16/30 ,  C23C16/515 ,  H01L21/312 ,  H01L21/316 ,  H01L21/31

CPC classification number: H01L21/02115 ,  C23C16/30 ,  C23C16/515 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/312 ,  H01L21/31633

Abstract: A method for depositing a low dielectric constant film is provided. The low dielectric constant film includes at least one silicon oxycarbide layer and at least one substantially silicon-free layer comprising carbon and hydrogen. The layers are deposited from a gas mixture including an organosilicon compound and a silicon-free hydrocarbon-based compound. The low dielectric constant film is deposited by a plasma process than includes pulses of RF power.

Abstract translation: 提供了一种沉积低介电常数膜的方法。 低介电常数膜包括至少一个碳氧化硅层和至少一个包含碳和氢的基本上无硅的层。 这些层由包括有机硅化合物和无硅烃基化合物的气体混合物沉积。 通过等离子体工艺沉积低介电常数膜，而不是包括RF功率的脉冲。