公开(公告)号：US20250126837A1

公开(公告)日：2025-04-17

申请号：US18990878

申请日：2024-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Cheng CHEN ,  Zhi-Chang LIN ,  Jung-Hung CHANG ,  Chien-Ning YAO ,  Tsung-Han CHUANG ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H10D30/67 ,  H01L21/762 ,  H10D30/01 ,  H10D84/83

Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.

公开(公告)号：US20250123449A1

公开(公告)日：2025-04-17

申请号：US18415784

申请日：2024-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Liang Shao ,  Yu-Sheng Huang ,  Chen-Hua Yu

IPC: G02B6/42

Abstract: A package includes an interposer, wherein the interposer includes a first waveguide and a first reflector that is optically coupled to the first waveguide; an optical package attached to the interposer, wherein the optical package includes a second waveguide; and a second reflector that is optically coupled to the second waveguide, wherein the second reflector is vertically aligned with the first reflector.

公开(公告)号：US12279451B2

公开(公告)日：2025-04-15

申请号：US17321996

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Chung-Chi Wen ,  Chia-Pin Lin

IPC: H01L21/02 ,  H10D30/01 ,  H10D30/67 ,  H10D30/69 ,  H10D62/00 ,  H10D62/10 ,  H10D62/832 ,  H10D64/01

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according one embodiment of the present disclosure include a plurality of channel members disposed over a substrate, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a source/drain feature. The source/drain feature includes a first epitaxial layer in contact with the substrate and the plurality of channel members, and a second epitaxial layer in contact with the first epitaxial layer and the plurality of inner spacer features. The first epitaxial layer and the second epitaxial layer include silicon germanium. A germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.

公开(公告)号：US12278287B2

公开(公告)日：2025-04-15

申请号：US18175346

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US12278259B2

公开(公告)日：2025-04-15

申请号：US18232332

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Wei Kuo ,  Chewn-Pu Jou ,  Huan-Neng Chen ,  Lan-Chou Cho ,  Robert Bogdan Staszewski

IPC: H01L23/522 ,  B01D1/00 ,  B01D1/12 ,  C02F1/04 ,  C02F11/12 ,  C02F11/18 ,  H01F27/28 ,  H01L49/02 ,  H03L7/085 ,  H03L7/099 ,  C02F101/30 ,  C02F103/14 ,  C02F103/16 ,  C02F103/28 ,  C02F103/32 ,  C02F103/34 ,  C02F103/36

Abstract: In an embodiment, a circuit includes: a transformer defining an inductive footprint within a first layer; a grounded shield bounded by the inductive footprint within a second layer separate from the first layer; and a circuit component bounded by the inductive footprint within a third layer separate from the second layer, wherein: the circuit component is coupled with the transformer through the second layer, and the third layer is separated from the first layer by the second layer.

公开(公告)号：US12276923B2

公开(公告)日：2025-04-15

申请号：US18673669

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Fu Lin ,  Shih-Chang Shih ,  Chia-Chen Chen

IPC: G03F7/00 ,  B01D53/04 ,  B01D53/30 ,  C23C16/44

Abstract: An exhaust system for discharging from semiconductor manufacturing equipment a hazardous gas includes: a main exhaust pipe above the semiconductor manufacturing equipment and having a top surface on a first side and a bottom surface on a second side, a first branch pipe connected to a source of a gas mixture containing the hazardous gas on the second side and connected to the main exhaust pipe through the top surface, a second branch pipe connected to a gas box on the second side and connected to the main exhaust pipe through the bottom surface, and a detector on the second branch pipe configured to detect presence of the hazardous gas and downstream to the gas box. The first and the second branch pipes are connected to the main exhaust pipe at a first location and a second location, respectively. The first location is more upstream than the second location.

公开(公告)号：US20250118679A1

公开(公告)日：2025-04-10

申请号：US18483657

申请日：2023-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiung PENG ,  Shih-Chi FU ,  Kuei-Shun CHEN ,  Yu-Lun LIU

IPC: H01L23/544 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/8234

Abstract: A method includes: forming a first mask over a substrate; forming first openings and a second opening in the first mask; forming first wells in first regions of the substrate exposed by the first openings and an alignment implant in a second region of the substrate exposed by the second opening; forming an alignment mark by recessing the alignment implant; and patterning a multi-layer semiconductor lattice under alignment of the alignment mark.

公开(公告)号：US20250117642A1

公开(公告)日：2025-04-10

申请号：US18983284

申请日：2024-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Win-San KHWA ,  Yu-Der CHIH ,  Yi-Chun SHIH ,  Chien-Yin LIU

IPC: G06N3/063 ,  G06N3/08 ,  G11C7/10 ,  G11C11/54 ,  G11C29/04

Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

公开(公告)号：US12272725B2

公开(公告)日：2025-04-08

申请号：US18341498

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Jyun-Ying Lin ,  Hsin-Li Cheng ,  Jing-Hwang Yang ,  Felix Ying-Kit Tsui ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L21/027 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/764 ,  H01L23/00 ,  H01L27/01 ,  H01L29/66 ,  H01L29/94 ,  H10B12/00 ,  H01L27/08

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

公开(公告)号：US12272708B2

公开(公告)日：2025-04-08

申请号：US18075323

申请日：2022-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiu-Ko Jangjian ,  Chih-Nan Wu ,  Chun-Che Lin ,  Yu-Ku Lin

IPC: H01L27/146

Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The photo sensitive regions are in the semiconductor substrate. The dielectric layer is over a backside surface of the semiconductor substrate. The grid structure is over a backside surface of the dielectric layer. The grid structure includes a plurality of grid lines. Each of the grid lines comprises a lower portion and an upper portion forming an interface with the lower portion. The convex dielectric lenses are alternately arranged with the grid lines over the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are higher than an interface between the upper portion and the lower portion of each of the grid lines.