公开(公告)号：US20150270120A1

公开(公告)日：2015-09-24

申请号：US14484511

申请日：2014-09-12

Applicant: Wei-E Wang ,  Mark Stephen Rodder

Inventor： Wei-E Wang ,  Mark Stephen Rodder

IPC: H01L21/02 ,  H01L21/324 ,  H01L29/165 ,  H01L21/3063

CPC classification number: H01L21/0262 ,  H01L21/02373 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/02658 ,  H01L21/3063 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/786

Abstract: Methods of forming strain-relaxing semiconductor layers are provided in which a porous region is formed in a surface of a semiconductor substrate. A first semiconductor layer that is lattice-matched with the semiconductor substrate is formed on the porous region. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer being a strained layer as formed. The second semiconductor layer is then relaxed.

Abstract translation: 提供形成应变松弛半导体层的方法，其中在半导体衬底的表面中形成多孔区。 在多孔区域上形成与半导体衬底晶格匹配的第一半导体层。 第二半导体层形成在第一半导体层上，第二半导体层是形成的应变层。 然后放松第二半导体层。

公开(公告)号：US20140054549A1

公开(公告)日：2014-02-27

申请号：US13592805

申请日：2012-08-23

Applicant: Wei-Yip LOH ,  Wei-E WANG

Inventor： Wei-Yip LOH ,  Wei-E WANG

IPC: H01L29/775 ,  H01L21/20

CPC classification number: H01L29/66356 ,  H01L29/205 ,  H01L29/7391

Abstract: A semiconductor device and tunnel field-effect transistor, and methods of fabrication thereof are provided. The device includes first and second semiconductor regions, an intermediate region, and an epitaxial layer. The intermediate region separates the first and second semiconductor regions, and the epitaxial layer extends at least partially between the first and second regions over or alongside of the intermediate region. A gate electrode is provided for gating the circuit structure. The epitaxial layer is disposed to reside between the gate electrode and at least one of the first semiconductor region, the second semiconductor region, or the intermediate region. The epitaxial layer includes an epitaxially-grown, ultra-thin body layer of semiconductor material with a thickness less than or equal to 15 nanometers. Where the semiconductor device is a tunneling field-effect transistor, the intermediate region may be a large band-gap semiconductor region, with a band-gap greater than that of the epitaxial layer.

Abstract translation: 提供半导体器件和隧道场效应晶体管及其制造方法。 该器件包括第一和第二半导体区域，中间区域和外延层。 中间区域分离第一和第二半导体区域，并且外延层至少部分地在第一和第二区域之间在中间区域的上方或旁边延伸。 提供栅电极用于选通电路结构。 外延层被设置为位于栅电极和第一半导体区域，第二半导体区域或中间区域中的至少一个之间。 外延层包括厚度小于或等于15纳米的外延生长的半导体材料超薄体层。 在半导体器件是隧道场效应晶体管的情况下，中间区域可以是大的带隙半导体区域，其带隙大于外延层的带隙。

公开(公告)号：US20120032234A1

公开(公告)日：2012-02-09

申请号：US13198959

申请日：2011-08-05

Applicant: Gang Wang ,  Matty Caymax ,  Maarten Leys ,  Wei-E Wang ,  Niamh Waldron

Inventor： Gang Wang ,  Matty Caymax ,  Maarten Leys ,  Wei-E Wang ,  Niamh Waldron

IPC: H01L21/20 ,  H01L29/267

CPC classification number: H01L21/02538 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/02639

Abstract: Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface. The method further comprises at least partially filling the recessed region with a III-V compound semiconductor material overlaying the surface.

Abstract translation: 公开了制造III-V族化合物半导体材料的方法以及如此制造的半导体材料。 在一个实施例中，该方法包括提供包括具有{001}取向的第一半导体材料和覆盖第一半导体材料的绝缘层的衬底。 绝缘层包括露出第一半导体材料的暴露区域的凹陷区域。 该方法还包括形成覆盖包括IV族半导体材料的暴露区域的缓冲层。 该方法还包括对衬底和缓冲层进行热退火，由此粗糙化缓冲层以产生具有阶梯密度和台阶高度的圆形的双阶梯形表面。 台阶密度和台阶高度的乘积在表面上大于或等于0.05。 该方法还包括用覆盖该表面的III-V族化合物半导体材料至少部分地填充该凹陷区域。

公开(公告)号：US08524562B2

公开(公告)日：2013-09-03

申请号：US12560282

申请日：2009-09-15

Applicant: Wei-E Wang ,  Han Chung Lin ,  Marc Meuris

Inventor： Wei-E Wang ,  Han Chung Lin ,  Marc Meuris

IPC: H01L21/336

CPC classification number: H01L21/3003 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/3006 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/78

Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.

Abstract translation: 在金属氧化物半导体（MOS）器件中的诸如Ge和III-V化合物（例如GaAs或InGaAs）的高迁移率半导体化合物通道中减少（避免）费米能级固定（FLP）的方法。 该方法使用原子氢，其使高迁移率半导体化合物的界面与栅极电介质钝化，并进一步修复缺陷。 该方法进一步改善了MOS器件特性，使得产生具有量子阱的MOS器件。

公开(公告)号：US08160052B2

公开(公告)日：2012-04-17

申请号：US12108268

申请日：2008-04-23

Applicant: Wei E ,  Rui Xu

Inventor： Wei E ,  Rui Xu

IPC: H04J3/06

CPC classification number: H04L41/5019 ,  H04L47/781 ,  H04L65/1069

Abstract: A method, a system and an apparatus for synchronizing the stream between the bearer control layer and bearer layer devices. Bearer layer device returns information corresponding to the stream synchronizing information distributed by the resource manager RM of the bearer control layer back to the resource manager RM (101, 102); when the resource manager RM determines that there is information needed to be synchronized included in the information returned by bearer layer device (103), it compares the information with the one held by itself (105), and performs synchronization to the information within the bearer layer devices that need to be synchronized according to the result of the comparison.

Abstract translation: 一种用于在承载控制层和承载层设备之间同步流的方法，系统和装置。 承载层设备将与承载控制层的资源管理器RM分配的流同步信息相对应的信息返回给资源管理器RM（101,102）; 当资源管理器RM确定需要被同步的信息包含在由承载层设备（103）返回的信息中时，它将该信息与其本身保持的信息进行比较（105），并且对承载层内的信息进行同步 需要根据比较结果进行同步的层设备。

公开(公告)号：US20100065824A1

公开(公告)日：2010-03-18

申请号：US12560282

申请日：2009-09-15

Applicant: Wei-E Wang ,  Han Chung Lin ,  Marc Meuris

Inventor： Wei-E Wang ,  Han Chung Lin ,  Marc Meuris

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L21/3003 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28255 ,  H01L21/28264 ,  H01L21/3006 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/78

Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.

Abstract translation: 在金属氧化物半导体（MOS）器件中的诸如Ge和III-V化合物（例如GaAs或InGaAs）的高迁移率半导体化合物通道中减少（避免）费米能级固定（FLP）的方法。 该方法使用原子氢，其使高迁移率半导体化合物的界面与栅极电介质钝化，并进一步修复缺陷。 该方法进一步改善了MOS器件特性，使得产生具有量子阱的MOS器件。

公开(公告)号：US20060253611A1

公开(公告)日：2006-11-09

申请号：US11398558

申请日：2006-04-06

Applicant: Chih-Lin Hu ,  Wei-E Jiang ,  Wei-Nan Tseng

Inventor： Chih-Lin Hu ,  Wei-E Jiang ,  Wei-Nan Tseng

IPC: G06F15/16

CPC classification number: H04L61/2015 ,  H04L29/1232 ,  H04L61/2092

Abstract: A method for network address transition. A number of electronic apparatuses connecting to a network is detected. It is determined whether a predetermined number exceeds or equals the detected number of electronic apparatuses. If the predetermined number exceeds or equals the detected number, a response function utilized to reply with an address in a specific subnet to a request message from the first electronic device is enabled. The request message is utilized to acquire an address in the subnet.

Abstract translation: 一种网络地址转换的方法。 检测到连接到网络的多个电子设备。 确定预定数量是否超过或等于所检测的电子设备的数量。 如果预定数量超过或等于检测到的数量，则能够将来自第一电子设备的特定子网中的地址用于回复请求消息的响应功能。 该请求消息用于获取子网中的地址。

公开(公告)号：US06969568B2

公开(公告)日：2005-11-29

申请号：US10766205

申请日：2004-01-28

Applicant: Shahid Rauf ,  Peter L. G. Ventzek ,  Wei E. Wu

Inventor： Shahid Rauf ,  Peter L. G. Ventzek ,  Wei E. Wu

IPC: G03F1/00 ,  H01L21/302 ,  H01L21/311

CPC classification number: G03F1/34 ,  H01L21/31116

Abstract: A chromeless phase lithography mask (30) that does not require photoresist to manufacture has a quartz substrate (32) is etched by using a plasma (38) containing one of a nitrogen augmented hydro-fluorocarbon oxygen mixture and a nitrogen augmented fluorocarbon oxygen mixture. Various hydro-fluorocarbons or fluorocarbons may be used. The nitrogen addition results in etched openings in the quartz substrate that have substantially vertical sidewalls in a uniform manner across the substrate. Surface roughness is minimized and edges of the openings are well-defined with minimal rounding. The etch rate is rendered controllable by reducing bias power without degrading a desired vertical sidewall profile.

Abstract translation: 不需要光致抗蚀剂的无铬相光刻掩模（30）通过使用包含氮增强的氢氟烃氧混合物和氮增强氟碳氧混合物之一的等离子体（38）进行蚀刻。 可以使用各种氢氟烃或碳氟化合物。 氮气添加导致在石英衬底中蚀刻的开口具有穿过衬底的均匀方式的基本上垂直的侧壁。 表面粗糙度最小化，并且开口的边缘被很好地限定在最小的四舍五入。 通过降低偏置功率而不降低期望的垂直侧壁轮廓，使蚀刻速率变得可控。

公开(公告)号：US06818362B1

公开(公告)日：2004-11-16

申请号：US10782566

申请日：2004-02-19

Applicant: Kevin D. Lucas ,  Robert E. Boone ,  Lloyd C. Litt ,  Wei E. Wu

Inventor： Kevin D. Lucas ,  Robert E. Boone ,  Lloyd C. Litt ,  Wei E. Wu

IPC: G03F900

CPC classification number: G03F1/26 ,  G03F1/30 ,  G03F1/68

Abstract: A method of generating a design of a reticle for a photolithography process. The reticle may include phase shift features, binary features, and mixed features. The method includes generating a reticle design from a pattern layout and then optimizing the reticle design. In some examples, generating the reticle design includes binning the features of the layout based on feature width. Examples of optimization operations include an over/under operation, an under/over operation, a feature segment expansion operation, a feature edge portion conversation from a binary portion to a phase shift portion, a corner binary segment expansion, a discontinuity removal operation, and a feature dimension change operation that includes a determination of a Mask Error Factor (MEF).

Abstract translation: 一种产生光刻工艺的掩模版设计的方法。 标线片可以包括相移特征，二进制特征和混合特征。 该方法包括从图案布局生成掩模版设计，然后优化掩模版设计。 在一些示例中，生成掩模版设计包括基于特征宽度来组合布局的特征。 优化操作的示例包括过/下操作，下/过操作，特征段扩展操作，从二进制部分到相移部分的特征边缘部分对话，角二进制段扩展，不连续删除操作和 特征尺寸变化操作，其包括掩模误差因子（MEF）的确定。

公开(公告)号：US06759675B2

公开(公告)日：2004-07-06

申请号：US09994182

申请日：2001-11-26

Applicant: Sebastian Csutak ,  Wei E. Wu

Inventor： Sebastian Csutak ,  Wei E. Wu

IPC: H01L2106

CPC classification number: H01L27/1446 ,  G02B5/18 ,  H01L31/02327

Abstract: An optical device uses one or more doped pockets in one embodiment to increase the electric field at one or more edges of the light absorbing region to increase the efficiency of the optical device. In alternate embodiments, the optical device uses an overlying light-barrier layer to reduce optical absorption within the more highly doped region. Some embodiments use a comb-like structure for the optical device to reduce capacitance and create a planar CMOS compatible structure.

Abstract translation: 光学器件在一个实施例中使用一个或多个掺杂的凹穴来增加光吸收区域的一个或多个边缘处的电场，以提高光学器件的效率。 在替代实施例中，光学器件使用覆盖的光阻层降低更高掺杂区域内的光吸收。 一些实施例使用用于光学装置的梳状结构来减小电容并产生平面CMOS兼容结构。