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62 条记录 (耗时 0.028 秒)

    Layout method of decoupling capacitors
    11.
    发明授权
    Layout method of decoupling capacitors 有权
    去耦电容布局方法

    公开(公告)号：US07222320B2

    公开(公告)日：2007-05-22

    申请号：US11023829

    申请日：2004-12-29

    申请人： Yasushige Ogawa

    发明人： Yasushige Ogawa

    IPC分类号： G06F17/50

    CPC分类号： H01L23/50 ,  G06F17/5072 ,  G06F17/5081 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A layout method of decoupling capacitors while ensuring the decoupling capacitance necessary for each grid area. The method includes calculating the total power consumption of logic cells, arranging the decoupling capacitance throughout the subject area in correspondence with the total power consumption, dividing the subject area into a plurality of grid areas, arranging the logic cells in each grid area, determining whether the decoupling capacitance is sufficient in each grid area for the logic cells in that grid area, and performing a supplementing process of the decoupling capacitance based on whether the decoupling capacitance is sufficient.

    摘要翻译： 一种去耦电容器的布局方法，同时确保每个栅格区域所需的去耦电容。 该方法包括计算逻辑单元的总功耗，对应于总功耗排列整个对象区域的去耦电容，将主区划分为多个网格区域，将逻辑单元布置在每个网格区域中，确定是否 在该网格区域中的逻辑单元的每个网格区域中去耦电容就足够了，并且基于去耦电容是否足够来执行去耦电容的补充处理。

    Semiconductor device having logic circuit and macro circuit
    12.
    发明授权
    Semiconductor device having logic circuit and macro circuit 失效
    具有逻辑电路和宏电路的半导体器件

    公开(公告)号：US07078945B2

    公开(公告)日：2006-07-18

    申请号：US11045104

    申请日：2005-01-31

    申请人： Yasushige Ogawa ,  Yoshiyuki Ishida

    发明人： Yasushige Ogawa ,  Yoshiyuki Ishida

    IPC分类号： H03L7/00

    CPC分类号： G11C29/12005 ,  G11C7/1006 ,  G11C7/22 ,  G11C29/02 ,  G11C2029/0401 ,  G11C2029/5006 ,  G11C2207/2227

    摘要： A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.

    摘要翻译： 半导体器件包括逻辑电路和宏电路。 宏电路包括消耗直流（DC）电路。 为了节省电力并允许测试，可以通过停止信号停止由电流消耗电路消耗的DC，从而停止宏电路的操作。 宏电路可以重启或恢复正常工作模式，而不会由于宏电路停止而引起误差。

    Control circuit for DC-DC converter in semiconductor integrated circuit device
    13.
    发明申请
    Control circuit for DC-DC converter in semiconductor integrated circuit device 失效
    半导体集成电路器件中DC-DC转换器的控制电路

    公开(公告)号：US20060139820A1

    公开(公告)日：2006-06-29

    申请号：US11101473

    申请日：2005-04-08

    申请人： Hidekiyo Ozawa ,  Hidenobu Ito ,  Chikara Tsuchiya ,  Yasushige Ogawa

    发明人： Hidekiyo Ozawa ,  Hidenobu Ito ,  Chikara Tsuchiya ,  Yasushige Ogawa

    IPC分类号： H02H7/00

    CPC分类号： H02M3/158 ,  H02M3/156

    摘要： A DC-DC converter for generating power supply voltage differing from input voltage, while operating a semiconductor circuit at a predetermined speed regardless of differences between devices or changes in the operation environment. An output voltage control circuit compares an oscillation signal, which is provided from a ring oscillator of the semiconductor circuit, with a triangular wave signal, which is provided from an oscillator of the DC-DC converter, and changes the output voltage of the DC-DC converter in accordance with the comparison result. This substantially equalizes the oscillation signal of the ring oscillator with the triangular wave signal, which functions as a reference signal, and operates the semiconductor circuit at a speed that is in accordance with the triangular wave signal.

    摘要翻译： DC-DC转换器，用于产生与输入电压不同的电源电压，同时以预定速度操作半导体电路，而不管设备之间的差异或操作环境的改变。 输出电压控制电路将从半导体电路的环形振荡器提供的振荡信号与由DC-DC转换器的振荡器提供的三角波信号进行比较，并将DC- DC转换器根据比较结果。 这使得用作为参考信号的三角波信号实质上均衡环形振荡器的振荡信号，并以与三角波信号相应的速度操作半导体电路。

    Layout method of decoupling capacitors
    14.
    发明申请
    Layout method of decoupling capacitors 有权
    去耦电容布局方法

    公开(公告)号：US20060017135A1

    公开(公告)日：2006-01-26

    申请号：US11023829

    申请日：2004-12-29

    申请人： Yasushige Ogawa

    发明人： Yasushige Ogawa

    IPC分类号： G06F17/50 ,  H01L29/00

    CPC分类号： H01L23/50 ,  G06F17/5072 ,  G06F17/5081 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A layout method of decoupling capacitors while ensuring the decoupling capacitance necessary for each grid area. The method includes calculating the total power consumption of logic cells, arranging the decoupling capacitance throughout the subject area in correspondence with the total power consumption, dividing the subject area into a plurality of grid areas, arranging the logic cells in each grid area, determining whether the decoupling capacitance is sufficient in each grid area for the logic cells in that grid area, and performing a supplementing process of the decoupling capacitance based on whether the decoupling capacitance is sufficient.

    摘要翻译： 一种去耦电容器的布局方法，同时确保每个栅格区域所需的去耦电容。 该方法包括计算逻辑单元的总功耗，对应于总功耗排列整个对象区域的去耦电容，将主区划分为多个网格区域，将逻辑单元布置在每个网格区域中，确定是否 在该网格区域中的逻辑单元的每个网格区域中去耦电容就足够了，并且基于去耦电容是否足够来执行去耦电容的补充处理。

    Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit
    15.
    发明授权
    Oscillator circuit, semiconductor device and semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit 有权
    振荡器电路，半导体器件和配有振荡电路的半导体存储器件，以及振荡电路的控制方法

    公开(公告)号：US06809605B2

    公开(公告)日：2004-10-26

    申请号：US10265101

    申请日：2002-10-07

    申请人： Yasushige Ogawa ,  Satoru Kawamoto

    发明人： Yasushige Ogawa ,  Satoru Kawamoto

    IPC分类号： H03B0100

    CPC分类号： G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067 ,  H03K3/012 ,  H03K3/014 ,  H03K3/0315 ,  H03K5/1252 ,  H03K5/19 ,  H03L3/00

    摘要： The present invention is made to resolve problems of the above described prior art. Prime object of the present invention is to provide an oscillator circuit capable of outputting oscillation signal with stable oscillation frequency, a semiconductor device and a semiconductor memory device provided with the oscillator circuit, and control method of the oscillator circuit. For achieving the prime object, there are taken the following countermeasures at the time of initiating oscillation where the inventive oscillator circuit can control to operate/stop oscillation. That is, the countermeasures to be taken are: (1) oscillation operation is stopped or an output of an oscillation signal is not permitted while transient oscillation frequency is unstable; or (2) a period that transient oscillation frequency is unstable is shortened.

    摘要翻译： 本发明是为了解决上述现有技术的问题而做出的。 本发明的主要目的是提供一种能够输出具有稳定振荡频率的振荡信号的振荡器电路，半导体器件和设置有振荡电路的半导体存储器件，以及振荡器电路的控制方法。 为了实现主要目的，在本发明的振荡器电路可以控制操作/停止振荡的启动振荡时采取以下对策。 也就是说，要采取的对策是：（1）暂态振荡频率不稳定时，振荡操作停止或振荡信号输出不允许; 或（2）瞬态振荡频率不稳定的时间缩短。

    Semiconductor integrated circuit device and data-write method thereof
    16.
    发明授权
    Semiconductor integrated circuit device and data-write method thereof 有权

    公开(公告)号：US06525975B2

    公开(公告)日：2003-02-25

    申请号：US09947459

    申请日：2001-09-07

    申请人： Kazumi Kojima ,  Yasushige Ogawa ,  Hiroyuki Sugamoto

    发明人： Kazumi Kojima ,  Yasushige Ogawa ,  Hiroyuki Sugamoto

    IPC分类号： G11C700

    CPC分类号： G11C7/22 ,  G11C11/4076

    摘要： There is intended to provide a semiconductor integrated circuit device capable of lowering the power consumption during data-write operation, enhancing operation speed, and reducing noises for stable operation. In the semiconductor integrated circuit, an active signal ACT to be inputted to a sense amplifier signal circuit SC1 is latched by a command latch circuit and outputted to a terminal N11. The terminal N11 outputs a control signal EDC1 via a timing adjusting circuit. The control signal EDC1 works to output a sense amplifier activating signal LE via a timing adjusting circuit and output buffer circuit and at the same time, the control signal EDC1 is outputted to a column switch signal circuit CS1. From the Column switch signal circuit CS1, a pulse signal is outputted via input of a control signal ACL, a pulse output circuit, and a terminal N13. In a logical circuit, AND processing is conducted between the pulse signal and an inversion signal of the control signal EDC1. Through a decode circuit, a resultant signal is outputted as switch signal CL, or CLM.

    Semiconductor memory device having bit line precharge circuits activated by separate control signals and control method for the same
    17.
    发明授权
    Semiconductor memory device having bit line precharge circuits activated by separate control signals and control method for the same 失效
    具有由分离的控制信号激活的位线预充电电路的半导体存储器件及其控制方法

    公开(公告)号：US06275431B1

    公开(公告)日：2001-08-14

    申请号：US09735481

    申请日：2000-12-14

    申请人： Kazumi Kojima ,  Yasushige Ogawa

    发明人： Kazumi Kojima ,  Yasushige Ogawa

    IPC分类号： G11C712

    CPC分类号： G11C7/12

    摘要： In a semiconductor memory device which is intended to lower the power consumption and raise the operation speed without increasing the circuit scale to meet trends toward the larger capacity, higher speed and, at the same time, the lower power voltage design, the precharge circuit Pre3 has its bit line shorting section formed of transistors TN1A and TN1B in series connection and its bit line voltage holding circuit formed of transistors TN2A and TN2B connected in series between the node of the transistors TN1A and TN1B and a precharge voltage VPR source, with the transistors TN1A and TN2A and the TN1B and TN2B being controlled by precharge signals BRS0 and BRS1, respectively. One of the precharge signals BRS0 and BRS1 is preset active since the former precharge operation cycle, the other precharge signal is activated to start the shorting operation of a bit line pair /BL-BL, and the preset precharge signal is deactivated to end the shorting operation.

    摘要翻译： 在半导体存储器件中，为了降低功耗并提高操作速度而不增加电路规模以满足趋向于较大容量，较高速度以及同时较低功率电压设计的趋势，预充电电路Pre3 具有串联连接的晶体管TN1A和TN1B形成的位线短路部分，并且其晶体管TN2A和TN2B串联连接在晶体管TN1A和TN1B的节点与预充电电压VPR源之间的位线电压保持电路与晶体管 TN1A和TN2A，TN1B和TN2B分别由预充电信号BRS0和BRS1控制。 预充电信号BRS0和BRS1之一被预置为有效，因为前一个预充电操作周期，另一个预充电信号被激活以开始位线对/ BL-BL的短路操作，并且预置的预充电信号被去激活以结束短路 操作。