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11.发明申请公开(公告)号：US20160189783A1
公开(公告)日：2016-06-30
申请号：US15066020
申请日：2016-03-10
Applicant: Apple Inc.
Inventor： Arik Rizel , Avraham Poza Meir , Yael Shur , Eyal Gurgi , Barak Baum
CPC classification number: G11C16/24 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/10 , G11C16/26 , H01L27/11568 , H01L29/42328
Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
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12.发明授权公开(公告)号：US09378809B1
公开(公告)日：2016-06-28
申请号：US14818328
申请日：2015-08-05
Applicant: APPLE INC.
Inventor： Charan Srinivasan , Eyal Gurgi
CPC classification number: G11C7/00 , G11C11/5628 , G11C16/3459 , G11C27/005 , G11C2211/5621
Abstract: A method for data storage includes setting a plurality of memory cells to hold respective target analog values, by applying to the memory cells a sequence of iterations, each iteration includes attempting to set the target analog values and then verifying whether the target analog values have been reached in accordance with a verification condition. After applying a predefined number of the iterations, the verification condition is relaxed and a condition of whether the target analog values have been reached in accordance with the relaxed verification condition is verified.
Abstract translation: 一种用于数据存储的方法包括设置多个存储器单元以保持各自的目标模拟值，通过向存储器单元施加一系列迭代，每次迭代包括尝试设置目标模拟值，然后验证目标模拟值是否已被 按照验证条件达成。 在应用预定数量的迭代之后，验证验证条件被放宽，并且验证是否已经根据放宽的验证条件达到目标模拟值的条件。
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公开(公告)号：US09361951B2
公开(公告)日：2016-06-07
申请号：US14468661
申请日：2014-08-26
Applicant: Apple Inc.
Inventor： Naftali Sommer , Stas Mouler , Eyal Gurgi , Yoav Kasorla , Liran Erez
CPC classification number: G11C5/14 , G11C5/145 , G11C5/147 , G11C16/10 , G11C16/12 , G11C16/30 , G11C16/32
Abstract: A method includes, in a storage system that includes multiple memory devices, holding a definition of a given type of storage command. Multiple storage commands of the given type are executed in the memory devices, such that an actual current consumption of each storage command deviates from a nominal current waveform defined for the given type by no more than a predefined deviation, and such that each storage command is preceded by a random delay.
Abstract translation: 一种方法包括在包括多个存储设备的存储系统中，保持给定类型的存储命令的定义。 给定类型的多个存储命令在存储器件中被执行，使得每个存储命令的实际电流消耗偏离为给定类型定义的额定电流波形不超过预定义的偏差，并且使得每个存储命令是 之前是随机延迟。
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公开(公告)号：US20160062907A1
公开(公告)日：2016-03-03
申请号：US14475609
申请日：2014-09-03
Applicant: Apple Inc.
Inventor： Stas Mouler , Shai Ojalvo , Yoav Kasorla , Eyal Gurgi
IPC: G06F12/10
CPC classification number: G06F12/0246 , G06F2212/1024 , G06F2212/1032 , G06F2212/7202 , G06F2212/7206 , G11C7/1006 , G11C11/5628 , G11C2211/5641
Abstract: A method for data storage includes defining an end-to-end mapping between data bits to be stored in a memory device that includes multiple memory cells and predefined programming levels. The data bits are mapped into mapped bits, so that the number of the mapped bits is smaller than the number of the data bits. The data bits are stored in the memory device by programming the mapped bits in the memory cells using a programming scheme that guarantees the end-to-end mapping. After storing the data bits, the data bits are read from the memory device in accordance with the end-to-end mapping.
Abstract translation: 一种用于数据存储的方法包括定义要存储在包括多个存储器单元和预定义编程级别的存储器件中的数据位之间的端对端映射。 数据位被映射到映射比特中，使得映射比特的数量小于数据比特数。 通过使用保证端对端映射的编程方案对存储器单元中的映射位进行编程，将数据位存储在存储器件中。 在存储数据位之后，根据端对端映射从存储器件读取数据位。
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公开(公告)号：US20160034341A1
公开(公告)日：2016-02-04
申请号：US14447114
申请日：2014-07-30
Applicant: Apple Inc.
Inventor： Shai Ojalvo , Yair Schwartz , Eyal Gurgi , Yoav Kasorla
CPC classification number: G06F11/1008 , G06F3/0619 , G06F3/064 , G06F3/0688 , G06F3/0689 , G06F11/1076 , G06F11/1096 , G11C29/00
Abstract: A system for data storage includes one or more non-volatile memory (NVM) devices, each device including multiple memory blocks, and a processor. The processor is configured to assign the memory blocks into groups, to apply a redundant data storage scheme in each of the groups, to identify a group of the memory blocks including at least one bad block that renders remaining memory blocks in the group orphan blocks, to select a type of data suitable for storage in the orphan blocks, and to store the data of the identified type in the orphan blocks.
Abstract translation: 用于数据存储的系统包括一个或多个非易失性存储器（NVM）设备，每个设备包括多个存储器块，以及处理器。 处理器被配置为将存储块分配成组，以在每个组中应用冗余数据存储方案，以识别包括至少一个在组孤立块中呈现剩余存储块的坏块的存储器块组， 选择适合在孤儿块中存储的数据类型，并将识别类型的数据存储在孤儿块中。
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Patent Agency Ranking
公开(公告)号：US09230680B2
公开(公告)日：2016-01-05
申请号：US14450903
申请日：2014-08-04
Applicant: Apple Inc.
Inventor： Yael Shur , Yoav Kasorla , Eyal Gurgi
CPC classification number: G11C27/00 , G11C7/00 , G11C13/0002 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/10 , G11C16/26 , G11C16/32 , G11C27/005
Abstract: A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration.
Abstract translation: 一种方法包括在与各个字线相关联的行中排列的模拟存储器单元的阵列中，读取选定字线中的第一组存储器单元，包括存储至少一个状态的一个或多个存储器单元 数组中除字线以外的所选字线。 响应于读取状态设置第二组存储器单元的读出配置。 使用读出配置读取第二组存储单元。
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公开(公告)号：US20150355858A1
公开(公告)日：2015-12-10
申请号：US14821008
申请日：2015-08-07
Applicant: Apple Inc.
Inventor： Shai Ojalvo , Eyal Gurgi , Yoav Kasorla
CPC classification number: G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0683 , G06F11/008 , G06F11/1012 , G06F11/1044 , G06F11/1068 , G06F11/1076 , G11C29/52
Abstract: A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, and applying ECC decoding to the recovered data using the reliability metrics. The recovered data is re-programmed.
Abstract translation: 一种方法包括通过将数据缓冲在易失性缓冲器中来将数据编码的纠错码（ECC）存储在模拟存储器单元中，然后将缓冲的数据写入模拟存储器单元，同时重写易失性缓冲器中的至少一些数据 有成功迹象。 在检测到将缓冲数据写入模拟存储器单元的故障时，通过读取易失性缓冲器和模拟存储器单元来产生恢复的数据，根据是否从 易失性缓冲器或来自模拟存储器单元，以及使用可靠性度量将ECC解码应用于恢复的数据。 恢复的数据被重新编程。
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公开(公告)号：US20150332782A1
公开(公告)日：2015-11-19
申请号：US14811103
申请日：2015-07-28
Applicant: Apple Inc.
Inventor： Eyal Gurgi , Micha Anholt , Yoav Kasorla
CPC classification number: G11C16/3427 , G06F3/0614 , G06F3/0653 , G06F3/0673 , G06F12/0238 , G06F12/0246 , G06F2212/1044 , G06F2212/7203 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3431
Abstract: A method in a memory that includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration, includes identifying multiple groups of potentially-interfering memory cells that potentially cause interference to a group of target memory cells. Partial distortion components, which are inflicted by the respective groups of the potentially-interfering memory cells on the target memory cells, are estimated. The partial distortion components are progressively accumulated so as to produce an estimated composite distortion affecting the target memory cells, while retaining only the composite distortion and not the partial distortion components. The target memory cells are read, and the interference in the target memory cells is canceled based on the estimated composite distortion.
Abstract translation: 包括以三维（3-D）配置排列的多个模拟存储器单元的存储器中的方法包括识别潜在地对一组目标存储器单元造成干扰的潜在干扰存储器单元的多个组。 估计由目标存储器单元上的潜在干扰存储器单元的相应组造成的部分失真分量。 逐渐积累部分失真分量，以产生影响目标存储器单元的估计复合失真，同时仅保留复合失真而不保留部分失真分量。 读取目标存储器单元，并且基于估计的复合失真来消除目标存储器单元中的干扰。
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公开(公告)号：US20150193293A1
公开(公告)日：2015-07-09
申请号：US14662470
申请日：2015-03-19
Applicant: Apple Inc.
Inventor： Eyal Gurgi , Yoav Kasorla , Barak Rotbard , Shai Ojalvo
IPC: G06F11/07
CPC classification number: G11C29/38 , G06F11/07 , G06F11/073 , G06F11/0772 , G06F11/263 , G11C11/1677 , G11C11/5628 , G11C11/5635 , G11C11/5678 , G11C13/0035 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C16/10 , G11C16/3459 , G11C29/12015 , G11C29/44 , G11C29/50012
Abstract: A method for data storage includes receiving in a memory device data for storage in a group of memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.
Abstract translation: 一种用于数据存储的方法包括在存储器装置中接收用于存储在一组存储器单元中的数据。 通过执行程序和验证（P＆V）过程将数据存储在组中，该过程适用于组中的存储器单元的编程脉冲序列，并将组中的存储器单元的各自的模拟值与相应的验证阈值进行比较。 在P＆V进程成功完成之后，在存储器件中检测到存储的数据与接收到的数据之间的不匹配。 响应于不匹配报告数据存储错误。
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公开(公告)号：US08897065B2
公开(公告)日：2014-11-25
申请号：US14257268
申请日：2014-04-21
Applicant: Apple Inc.
Inventor： Yoav Kasorla , Eyal Gurgi , Dotan Sokolov , Ofir Shalvi
CPC classification number: G06F11/1072 , G06F12/0246 , G06F12/0607 , G06F2212/7208 , G11C29/52
Abstract: A method for data storage includes initially storing a sequence of data pages in a memory that includes multiple memory arrays, such that successive data pages in the sequence are stored in alternation in a first number of the memory arrays. The initially-stored data pages are rearranged in the memory so as to store the successive data pages in the sequence in a second number of the memory arrays, which is less than the first number. The rearranged data pages are read from the second number of the memory arrays.
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