公开(公告)号：US20240393695A1

公开(公告)日：2024-11-28

申请号：US18792284

申请日：2024-08-01

Applicant: Applied Materials, Inc.

Inventor： Huixiong DAI ,  Srinivas D. NEMANI ,  Steven Hiloong WELCH ,  Mangesh Ashok BANGAR ,  Ellie Y. YIEH

IPC: G03F7/20 ,  G03F7/16 ,  G03F7/38 ,  H01L21/027 ,  H01L21/266 ,  H01L21/311

Abstract: A method for enhancing a photoresist profile control includes applying a photoresist layer comprising a photoacid generator on an underlayer disposed on a material layer, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and drifting photoacid from the photoresist layer to a predetermined portion of the underlayer under the first portion of the photoresist layer.

公开(公告)号：US20230389441A1

公开(公告)日：2023-11-30

申请号：US18231414

申请日：2023-08-08

Applicant: Applied Materials, Inc.

Inventor： Minrui YU ,  Wenhui WANG ,  Jaesoo AHN ,  Jong Mun KIM ,  Sahil PATEL ,  Lin XUE ,  Chando PARK ,  Mahendra PAKALA ,  Chentsau Chris YING ,  Huixiong DAI ,  Christopher S. NGAI

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10N50/10 ,  G01R33/098 ,  G11C11/161 ,  G01R33/095 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

公开(公告)号：US20210088896A1

公开(公告)日：2021-03-25

申请号：US16983093

申请日：2020-08-03

Applicant: Applied Materials, Inc.

Inventor： Huixiong DAI ,  Mangesh Ashok BANGAR ,  Pinkesh Rohit SHAH ,  Srinivas D. NEMANI ,  Steven Hiloong WELCH ,  Christopher Siu Wing NGAI ,  Ellie Y. YIEH

IPC: G03F1/36 ,  G03F7/38

Abstract: Embodiments of the disclosure relate to lithography simulation and optical proximity correction. Field-guided post exposure bake processes have enabled improved lithography performance and various parameters of such processes are included in the optical proximity correction models generated in accordance with the embodiments described herein. An optical proximity correction model includes one or more parameters of anisotropic acid etching characteristics, ion generation and/or movement, electron movement, hole movement, and chemical reaction characteristics.

公开(公告)号：US20200233307A1

公开(公告)日：2020-07-23

申请号：US16600101

申请日：2019-10-11

Applicant: Applied Materials, Inc.

Inventor： Huixiong DAI ,  Mangesh BANGAR ,  Christopher S. NGAI ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Steven Hiloong WELCH

IPC: G03F7/16 ,  G03F7/09 ,  G03F7/20

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

公开(公告)号：US20160005662A1

公开(公告)日：2016-01-07

申请号：US14736020

申请日：2015-06-10

Applicant: Applied Materials, Inc.

Inventor： Ellie Y. YIEH ,  Huixiong DAI ,  Srinivas D. NEMANI ,  Ludovic GODET ,  Christopher Dennis BENCHER

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/20

Abstract: Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system.

Abstract translation: 本公开的实施例提供了使用电子或离子注入的用于覆盖和边缘放置误差（EPE）的局部应力调制的装置和方法。 在一个实施例中，用于校正衬底上的覆盖误差的处理通常包括在衬底上的度量工具中执行测量过程以获得衬底失真或覆盖误差图，基于所述衬底失真或覆盖误差图确定掺杂参数以校正重叠误差或衬底失真 覆盖误差图，并且基于确定用于校正衬底失真或重叠误差的掺杂参数向掺杂装置提供掺杂配方。 实施例还可以使用确定的掺杂修复配方在衬底上执行掺杂处理过程，例如通过将覆盖误差图或衬底失真与存储在计算系统中的数据库进行比较。

公开(公告)号：US20150118832A1

公开(公告)日：2015-04-30

申请号：US14062638

申请日：2013-10-24

Applicant: Applied Materials, Inc.

Inventor： Bingxi Sun WOOD ,  Li Yan MIAO ,  Huixiong DAI ,  Adam BRAND ,  Yongmei CHEN ,  Mandar B. PANDIT ,  Qingjun ZHOU

IPC: H01L21/266 ,  H01L21/3105

CPC classification number: H01L21/266 ,  H01L21/26586 ,  H01L21/31053 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/66803

Abstract: Embodiments of the present invention provide a methods for patterning a hardmask layer with good process control for an ion implantation process, particularly suitable for manufacturing the fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of patterning a hardmask layer disposed on a substrate includes forming a planarization layer over a hardmask layer disposed on a substrate, disposing a patterned photoresist layer over the planarization layer, patterning the planarization layer and the hardmask layer uncovered by the patterned photoresist layer in a processing chamber, exposing a first portion of the underlying substrate, and removing the planarization layer from the substrate.

Abstract translation: 本发明的实施例提供了一种用于对具有用于离子注入工艺的良好工艺控制的硬掩模层图案化的方法，特别适用于制造用于半导体芯片的鳍式场效应晶体管（FinFET）。 在一个实施例中，图案化设置在衬底上的硬掩模层的方法包括在设置在衬底上的硬掩模层上形成平坦化层，在平坦化层上设置图案化的光致抗蚀剂层，将平坦化层和硬掩模层图案化， 在处理室中的图案化光致抗蚀剂层，暴露下面的衬底的第一部分，以及从衬底去除平坦化层。

公开(公告)号：US20140327117A1

公开(公告)日：2014-11-06

申请号：US14269010

申请日：2014-05-02

Applicant: Applied Materials, Inc.

Inventor： Christopher Dennis BENCHER ,  Daniel Lee DIEHL ,  Huixiong DAI ,  Yong CAO ,  Tingjun XU ,  Weimin (Wilson) ZENG ,  Peng XIE

IPC: H01L21/033

CPC classification number: H01L21/0337 ,  C23C14/0042 ,  C23C14/06 ,  C23C14/14 ,  C23C14/351 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02266 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31138 ,  H01L21/31144

Abstract: The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiOxNyCz:Hw, where w, x, y, and z can vary in concentration from 0% to 100%, is produced as a hardmask with optical properties that are substantially matched to the photo-resists at the exposure wavelength. Thus making the hardmask optically planarized with respect to the photo-resist. This allows for multiple sequences of litho and etches in the hardmask while the photo-resist maintains essentially no optical topography or reflectivity variations.

Abstract translation: 本文的实施方案提供了用于形成PVD氧化硅或富硅氧化物或PVD SiN或富硅SiN或富SiC或富硅SiC的方法或前述组合，包括将氢控制掺入到迄今为止参考的化合物 作为SiO x N y C z：H w，其中w，x，y和z可以在0％至100％的浓度范围内变化，作为具有与曝光波长下的光致抗蚀剂基本匹配的光学性质的硬掩模。 因此使相对于光致抗蚀剂光学平坦化的硬掩模。 这允许在硬掩模中的多个序列的光刻和蚀刻，而光致抗蚀剂基本上保持没有光学形貌或反射率变化。

公开(公告)号：US20240085810A1

公开(公告)日：2024-03-14

申请号：US18243129

申请日：2023-09-07

Applicant: Applied Materials, Inc.

Inventor： Huixiong DAI ,  Mangesh Ashok BANGAR ,  Chih-An HSU ,  Srinivas D. NEMANI ,  Dmitry LUBOMIRSKY ,  Ellie Y. YIEH

IPC: G03F7/00 ,  G03F7/40

CPC classification number: G03F7/70875 ,  G03F7/40

Abstract: A method and apparatus for performing post-exposure bake operations is described herein. After exposure of photoresist on a substrate, the substrate is heated during a baking process to facilitate protection of the resist. The baking process is performed in a vacuum environment at sub-atmospheric pressures. After baking at reduced pressure, the substrate is cooled. The cooling process is performed at sub-atmospheric pressures. Further development of the resist is performed at ambient pressures.

公开(公告)号：US20230229089A1

公开(公告)日：2023-07-20

申请号：US18188676

申请日：2023-03-23

Applicant: Applied Materials, Inc.

Inventor： Huixiong DAI ,  Mangesh Ashok BANGAR ,  Srinivas D. NEMANI ,  Ellie Y. YIEH ,  Steven Hiloong WELCH ,  Christopher S. NGAI

IPC: G03F7/039 ,  G03F7/004

CPC classification number: G03F7/0392 ,  G03F7/0045

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

公开(公告)号：US20220317579A1

公开(公告)日：2022-10-06

申请号：US17222696

申请日：2021-04-05

Applicant: Applied Materials, Inc.

Inventor： Mangesh Ashok BANGAR ,  Gautam PISHARODY ,  Lancelot HUANG ,  Alan L. TSO ,  Douglas A. BUCHBERGER, JR. ,  Huixiong DAI ,  Dmitry LUBOMIRSKY ,  Srinivas D. NEMANI ,  Christopher Siu Wing Ngai

IPC: G03F7/20

Abstract: Embodiments of the present disclosure generally relate to apparatus and methods for verification and re-use of process fluids. The apparatus generally includes a tool for performing lithography, and a recirculation path coupled to the tool. The recirculation path generally includes a collection unit coupled at first end to a first end of the tool, and a probe coupled at a first end to a second end of the collection unit, the probe for determining one or more characteristics of a fluid flowing from the tool. The recirculation path of the apparatus further generally includes a purification unit coupled at a first end to a third end of the collection unit, the purification unit further coupled at a second end to a second end of the probe, the purification unit for changing a characteristic of the fluid.