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    Apparatus and method for obfuscating power consumption of a processor
    11.
    发明授权
    Apparatus and method for obfuscating power consumption of a processor 有权

    公开(公告)号：US10255462B2

    公开(公告)日：2019-04-09

    申请号：US15185789

    申请日：2016-06-17

    Applicant: ARM Limited

    Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Carl Wayne Vineyard

    IPC: H04L29/06 ,  G06F21/75 ,  H04L9/00 ,  G09C1/00

    Abstract: An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

    CMOS Process Skew Sensor
    12.
    发明申请
    CMOS Process Skew Sensor 审中-公开

    公开(公告)号：US20190064259A1

    公开(公告)日：2019-02-28

    申请号：US15691722

    申请日：2017-08-30

    Applicant: ARM Limited

    Inventor： Bal S. Sandhu ,  George McNneil Lattimore

    IPC: G01R31/28 ,  H03K5/24

    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include converter circuitry that operates to provide a drive current. The integrated circuit may include process detector circuitry having multiple drive strength devices that are driven by the drive current from the converter circuitry. The multiple drive strength devices may provide multiple drive strength signals based on the drive current. The integrated circuit may include comparator circuitry having a comparator that receives the multiple drive strength signals from the multiple drive strength devices, detects a voltage difference between the multiple drive strength signals, and provides an output signal based on the detected voltage difference.

    Brown-out detector
    13.
    发明授权
    Brown-out detector 有权

    公开(公告)号：US10191527B2

    公开(公告)日：2019-01-29

    申请号：US14712614

    申请日：2015-05-14

    Applicant: ARM Limited

    Inventor： Bal S. Sandhu ,  James Edward Myers

    IPC: G01R31/40 ,  G01R19/165 ,  G06F1/28 ,  G01R19/32

    Abstract: Various implementations described herein are directed to an integrated circuit for brown-out detection. The integrated circuit may include a first stage configured to receive an input voltage and provide a first voltage independent of temperature while remaining related to the input voltage. The integrated circuit may include a second stage configured to receive the input voltage, receive the first voltage from the first stage, and up-convert the first voltage as input voltage lowers. The second stage may be configured to provide a second voltage corresponding to a differential voltage of the input voltage and the first voltage. The integrated circuit may include a third stage configured to receive the second voltage and provide a high-gain output voltage corresponding to an error signal.

    Monitoring Circuit and Method
    17.
    发明申请
    Monitoring Circuit and Method 审中-公开

    公开(公告)号：US20180150120A1

    公开(公告)日：2018-05-31

    申请号：US15361405

    申请日：2016-11-26

    Applicant: ARM Limited

    Inventor： Parameshwarappa Anand Kumar Savanth ,  Bal S. Sandhu ,  James Edward Myers ,  Alexander Stewart Weddell ,  David Walter Flynn

    IPC: G06F1/28 ,  G01R19/165

    CPC classification number: G06F1/28 ,  G01R19/16576

    Abstract: Broadly speaking, embodiments of the present techniques provide a voltage monitoring circuit for low power minimum-energy sensor nodes. The circuit comprises sensing circuitry to sense a monitored signal having a plurality of operating signal states; a first comparator having a first input for receiving an upper threshold signal; and a second comparator having a first input for receiving a lower threshold signal, the upper and lower threshold signals defining a range which includes at least one signal state of the plurality of operating states of the monitored signal, wherein the first and second comparators have a bias input for receiving a bias configuration setting, the bias configuration setting being selectable according to an operating signal state of the monitored signal.

    Apparatus and Method for Obfuscating Power Consumption of a Processor
    18.
    发明申请
    Apparatus and Method for Obfuscating Power Consumption of a Processor 审中-公开

    公开(公告)号：US20170364710A1

    公开(公告)日：2017-12-21

    申请号：US15185789

    申请日：2016-06-17

    Applicant: ARM Limited

    Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Carl Wayne Vineyard

    IPC: G06F21/75 ,  H04L9/00

    CPC classification number: G06F21/75 ,  G09C1/00 ,  H04L9/003 ,  H04L2209/125

    Abstract: An apparatus for obfuscating power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises counterbalance circuitry configured to provide a second power consumption to directly counterbalance the power consumption associated with the one or more operations of the logic circuitry. The second power consumption varies inversely with the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

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