公开(公告)号：US10978141B1

公开(公告)日：2021-04-13

申请号：US16698851

申请日：2019-11-27

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen ,  Vivek Asthana ,  Munish Kumar

IPC: G11C11/418 ,  G11C11/417 ,  G11C11/419

Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry, two or more memory instances coupled to the first and second word-line decoder circuitry; and a control block circuitry coupled to the first and second word-line decoder circuitry and the two or more memory instances. Also, a pin bus enabled in the control block circuitry may be configured to at least partially control selection of one or more of the two or more memory instances.

公开(公告)号：US10854280B2

公开(公告)日：2020-12-01

申请号：US15691001

申请日：2017-08-30

Applicant: ARM Limited

Inventor： Abhairaj Singh ,  Vivek Asthana ,  Monu Rathore ,  Ankur Goel ,  Nikhil Kaushik ,  Rachit Ahuja ,  Rahul Mathur ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C11/408 ,  G11C11/419 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

公开(公告)号：US20180331681A1

公开(公告)日：2018-11-15

申请号：US16042949

申请日：2018-07-23

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03K17/22 ,  G11C5/14

CPC classification number: H03K17/223 ,  G11C5/148

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

公开(公告)号：US10033376B2

公开(公告)日：2018-07-24

申请号：US15143197

申请日：2016-04-29

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03L7/00 ,  H03K17/22 ,  G11C5/14

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

公开(公告)号：US20230411351A1

公开(公告)日：2023-12-21

申请号：US17752560

申请日：2022-05-24

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Vivek Asthana ,  Ettore Amirante

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L23/481 ,  H01L2225/06541 ,  H01L21/76898 ,  H01L25/50 ,  H01L23/53228

Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through an input/output circuit of the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings at least partially in an input/output circuitry of the memory macro unit based on the determined dimensions of the memory macro unit.

公开(公告)号：US20210082496A1

公开(公告)日：2021-03-18

申请号：US17107559

申请日：2020-11-30

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Vivek Asthana ,  Ankur Garcia Goel ,  Nikhil Kaushik ,  Rachit Ahuja ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C11/419 ,  G11C11/418

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

公开(公告)号：US20190253084A1

公开(公告)日：2019-08-15

申请号：US15896015

申请日：2018-02-13

Applicant: Arm Limited

Inventor： Vivek Asthana ,  Jitendra Dasani ,  Amit Chhabra

IPC: H03M13/00 ,  G11C16/08 ,  G11C8/10 ,  G11C8/08

CPC classification number: H03M13/611 ,  G11C8/08 ,  G11C8/10 ,  G11C11/41 ,  G11C16/08

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include first decoding circuitry that receives an address and partially decodes the address to generate a partially decoded address. The integrated circuit may include second decoding circuitry that receives the partially decoded address, generates a decoded address, and provides the decoded address to a wordline. The integrated circuit may include encoding circuitry that receives the decoded address from the wordline and encodes the decoded address to generate an encoded address. The integrated circuit may include comparing circuitry that receives the encoded address and compares the encoded address with the address to detect faults in the memory circuitry.

公开(公告)号：US20190066772A1

公开(公告)日：2019-02-28

申请号：US15691001

申请日：2017-08-30

Applicant: ARM Limited

Inventor： Abhairaj Singh ,  Vivek Asthana ,  Monu Rathore ,  Ankur Goel ,  Nikhil Kaushik ,  Rachit Ahuja ,  Rahul Mathur ,  Bikas Maiti ,  Yew Keong Chong

IPC: G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

公开(公告)号：US10199094B2

公开(公告)日：2019-02-05

申请号：US15619332

申请日：2017-06-09

Applicant: ARM Limited

Inventor： Ankur Goel ,  Saikat Kumar Banik ,  Lokesh Kumar Saini ,  Vivek Asthana

IPC: G11C11/412 ,  G11C11/419 ,  H01L23/528 ,  H01L27/11 ,  G11C11/418

Abstract: A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.

公开(公告)号：US20180358086A1

公开(公告)日：2018-12-13

申请号：US15619332

申请日：2017-06-09

Applicant: ARM Limited

Inventor： Ankur Goel ,  Saikat Kumar Banik ,  Lokesh Kumar Saini ,  Vivek Asthana

IPC: G11C11/419 ,  H01L23/528 ,  H01L27/11 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418 ,  H01L23/528 ,  H01L27/1104

Abstract: A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.