利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

146 条记录 (耗时 0.041 秒)

    Phase change memory cell with vertical transistor
    11.
    发明授权
    Phase change memory cell with vertical transistor 有权
    具有垂直晶体管的相变存储单元

    公开(公告)号：US07932167B2

    公开(公告)日：2011-04-26

    申请号：US11771457

    申请日：2007-06-29

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles William Koburger, III ,  Chung Hon Lam

    IPC分类号： H01L21/44

    CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

    摘要： A memory cell in an integrated circuit is fabricated in part by forming a lower electrode feature, an island, a sacrificial feature, a gate feature, and a phase change feature. The island is formed on the lower electrode feature and has one or more sidewalls. It comprises a lower doped feature, a middle doped feature formed above the lower doped feature, and an upper doped feature formed above the middle doped feature. The sacrificial feature is formed above the island, while the gate feature is formed along each sidewall of the island. The gate feature overlies at least a portion of the middle doped feature of the island and is operative to control an electrical resistance therein. Finally, the phase feature is formed above the island at least in part by replacing at least a portion of the sacrificial feature with a phase change material. The phase change material is operative to switch between lower and higher electrical resistance states in response to an application of an electrical signal.

    摘要翻译： 部分地通过形成下电极特征，岛，牺牲特征，栅极特征和相变特征来制造集成电路中的存储单元。 岛形成在下电极特征上并具有一个或多个侧壁。 它包括下掺杂特征，形成在下掺杂特征之上的中掺杂特征，以及形成在中掺杂特征之上的上掺杂特征。 牺牲特征形成在岛上方，而栅极特征沿着岛的每个侧壁形成。 栅极特征覆盖岛的中间掺杂特征的至少一部分，并且可操作以控制其中的电阻。 最后，相位特征至少部分地通过用相变材料代替牺牲特征的至少一部分而在岛上方形成。 响应于电信号的应用，相变材料可操作以在较低和较高的电阻状态之间切换。

    Fill-in etching free pore device
    13.
    发明授权
    Fill-in etching free pore device 有权
    填充蚀刻自由孔装置

    公开(公告)号：US07879645B2

    公开(公告)日：2011-02-01

    申请号：US12020717

    申请日：2008-01-28

    申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch ,  Chieh Fang Chen

    发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch ,  Chieh Fang Chen

    IPC分类号： H01L21/06 ,  H01L21/44

    CPC分类号： H01L45/04 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L21/76808 ,  H01L21/76816 ,  H01L27/222 ,  H01L27/24 ,  H01L43/08 ,  H01L45/145

    摘要： A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.

    摘要翻译： 存储单元包括在底部电极层上方具有第一介电层的存储单元层，在第一介电层上的第二电介质层和位于第二介电层上的顶部电极。 电介质层限定具有由第一电极层和底部电极限定的第一部分和由第二电介质层和顶部电极限定的第二部分的通孔。 存储元件位于通孔内并与顶部和底部电极电接触。 通孔的第一和第二部分可以分别包括收缩的能量集中区和扩大区。 收缩区域可以具有小于用于形成通孔的扩大区域的过程的最小特征尺寸的宽度。 还公开了一种用于制造存储单元的方法。

    ELECTRODE FORMED IN APERTURE DEFINED BY A COPOLYMER MASK
    18.
    发明申请
    ELECTRODE FORMED IN APERTURE DEFINED BY A COPOLYMER MASK 审中-公开
    由共聚物掩模定义的电极中形成的电极

    公开(公告)号：US20090239334A1

    公开(公告)日：2009-09-24

    申请号：US12052581

    申请日：2008-03-20

    申请人： Matthew J. Breitwisch ,  Matthew Colburn ,  Eric Joseph ,  Chung Hon Lam ,  Deborah A. Neumayer ,  Alejandro G. Schrott

    发明人： Matthew J. Breitwisch ,  Matthew Colburn ,  Eric Joseph ,  Chung Hon Lam ,  Deborah A. Neumayer ,  Alejandro G. Schrott

    IPC分类号： H01L21/00

    CPC分类号： H01L45/1683 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

    摘要： A method of manufacturing a memory device is provided that in one embodiment includes providing an interlevel dielectric layer including a first via containing a memory material; forming at least one insulating layer on an upper surface of the memory material and the interlevel dielectric layer; forming an cavity through a portion of a thickness of the at least one insulating layer; forming a copolymer mask in at least the cavity, the copolymer mask including at least one opening that provides an exposed surface of a remaining portion of the at least one insulating layer that overlies the memory material; etching the exposed surface of the remaining portion of the at least one insulating layer to provide a second via to the memory material; and forming a conductive material within the second via in electrical contact with the memory material.

    摘要翻译： 提供了一种制造存储器件的方法，其在一个实施例中包括提供包括含有存储材料的第一通孔的层间介电层; 在所述存储材料和所述层间电介质层的上表面上形成至少一个绝缘层; 通过所述至少一个绝缘层的厚度的一部分形成空腔; 在至少所述空腔中形成共聚物掩模，所述共聚物掩模包括至少一个开口，所述至少一个开口提供覆盖所述存储材料的所述至少一个绝缘层的剩余部分的暴露表面; 蚀刻所述至少一个绝缘层的剩余部分的暴露表面以向所述存储材料提供第二通孔; 以及在所述第二通孔内与所述记忆材料电接触形成导电材料。

    METHOD TO ENHANCE PERFORMANCE OF COMPLEX METAL OXIDE PROGRAMMABLE MEMORY
    19.
    发明申请
    METHOD TO ENHANCE PERFORMANCE OF COMPLEX METAL OXIDE PROGRAMMABLE MEMORY 审中-公开
    提高复合金属氧化物可编程存储器性能的方法

    公开(公告)号：US20090186443A1

    公开(公告)日：2009-07-23

    申请号：US12017848

    申请日：2008-01-22

    申请人： Eric A. Joseph ,  Chung Hon Lam ,  Gerhard I. Meijer ,  Stephen M. Rossnagel ,  Alejandro Gabriel Schrott

    发明人： Eric A. Joseph ,  Chung Hon Lam ,  Gerhard I. Meijer ,  Stephen M. Rossnagel ,  Alejandro Gabriel Schrott

    IPC分类号： H01L21/34

    CPC分类号： H01L45/08 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/1273 ,  H01L45/147 ,  H01L45/16

    摘要： A method of incorporating oxygen vacancies near an electrode/oxide interface region of a complex metal oxide programmable memory cell which includes forming a first electrode of a metallic material which remains metallic upon oxidation, forming a second electrode facing the first electrode, forming an oxide layer in between the first and second electrodes, applying an electrical signal to the first electrode such that oxygen ions from the oxide layer are embedded in and oxidize the first electrode, and forming oxygen vacancies near the electrode/oxide interface region of the complex metal oxide programmable memory cell.

    摘要翻译： 一种在复合金属氧化物可编程存储单元的电极/氧化物界面区域附近引入氧空位的方法，其包括在氧化时形成保持金属的金属材料的第一电极，形成面向第一电极的第二电极，形成氧化物层 在第一和第二电极之间，向第一电极施加电信号，使得来自氧化物层的氧离子嵌入并氧化第一电极，并在复合金属氧化物可编程的电极/氧化物界面区域附近形成氧空位 记忆单元