公开(公告)号：US08207568B2

公开(公告)日：2012-06-26

申请号：US11162661

申请日：2005-09-19

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Keith E. Downes ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Robert M. Rassel ,  Anthony K. Stamper

IPC分类号： H01L29/92

CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L28/75

摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.

摘要翻译： 制造MIM电容器和MIM电容器的方法。 该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。 去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。 上板被切下，使得上板的边缘位于掩模下方。 使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

公开(公告)号：US07768055B2

公开(公告)日：2010-08-03

申请号：US11164634

申请日：2005-11-30

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Jonghae Kim ,  Jean-Oliver Plouchart ,  Anthony K. Stamper

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Jonghae Kim ,  Jean-Oliver Plouchart ,  Anthony K. Stamper

IPC分类号： H01L29/94

CPC分类号： H01L23/5228 ,  H01L23/5227 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/00

摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.

摘要翻译： 通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。 电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。 电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

公开(公告)号：US20090065898A1

公开(公告)日：2009-03-12

申请号：US12271942

申请日：2008-11-17

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

IPC分类号： H01L29/00

CPC分类号： H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

公开(公告)号：US07485540B2

公开(公告)日：2009-02-03

申请号：US11161832

申请日：2005-08-18

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John M. Cotte ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

IPC分类号： H01L21/20

CPC分类号： H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

摘要翻译： 在集成电路的后端形成电阻器的过程中，沉积中间介电层，并通过可蚀刻的量蚀刻通过该介质层并将其沉积到下介电层中，使得沉积在电介质层中的电阻层的顶部 沟槽的高度接近于下介电层的顶部; 沟槽被填充，沟槽外的电阻层被去除，然后沉积第二介电层。 通过第二电介质层以与电阻器接触的通孔的深度与下电介质层中的金属互连接触孔的深度相同。 使用三层电阻器结构，其中电阻膜夹在两个阻挡电阻器和BEOL ILD层之间的扩散的保护层之间。

公开(公告)号：US20080173976A1

公开(公告)日：2008-07-24

申请号：US11626548

申请日：2007-01-24

申请人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

发明人： Anthony K. Stamper ,  Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  William J. Murphy ,  Kunal Vaed

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/0688 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5227 ,  H01L23/53295 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

摘要翻译： 提供了一种用于制造微电子芯片的方法，该微电子芯片包括覆盖气隙的诸如电感器的无源器件。 在这种方法中，在微电子芯片的半导体区域中形成多个前端（“FEOL”）器件，并且形成多个层叠的层间电介质（“ILD”）层以覆盖多个 的多个层叠的ILD层，包括第一ILD层和第二ILD层，其中第二ILD层抵抗攻击第一ILD层的第一蚀刻剂的侵袭。 形成无源器件至少覆盖第一ILD层。 使用第一蚀刻剂，除去与无源器件对准的第一ILD层的一部分，以形成与被动器件对准的无源器件下方的气隙。

公开(公告)号：US07410894B2

公开(公告)日：2008-08-12

申请号：US11161217

申请日：2005-07-27

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John E. Florkey ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  John E. Florkey ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper ,  Kunal Vaed

IPC分类号： H01L21/44 ,  H01L21/20 ,  H01L29/00

CPC分类号： H01L21/76885 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5227 ,  H01L23/53238 ,  H01L28/10 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.

摘要翻译： 一种形成半导体结构的方法以及如此形成的半导体结构，其中诸如电感器的传输线形成在最后一个金属布线层的表面上方的平面上。

公开(公告)号：US20080122574A1

公开(公告)日：2008-05-29

申请号：US11458494

申请日：2006-07-19

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

IPC分类号： H01C1/06 ,  H01L21/20

CPC分类号： H01L27/0802 ,  H01L21/26513 ,  H01L28/20

摘要： A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.

摘要翻译： 含多晶硅的电阻器包括：（1）选自硼和二氟化硼的p掺杂剂; 和（2）选自砷和磷的n掺杂剂。 p掺杂剂和n掺杂剂中的每一个掺杂剂的掺杂剂浓度从每立方厘米约1e18至约1e21掺杂剂原子。 用于形成多晶硅电阻器的方法使用相对于每平方厘米约1e14至约1e16掺杂剂离子的注入剂量。 p掺杂剂和n掺杂剂可以同时或顺序地提供。 对于具有约100至约5000欧姆/平方的薄层电阻的多晶硅电阻器，该方法提供某些多晶硅电阻器的薄层电阻百分比标准偏差小于约1.5％。

公开(公告)号：US07691717B2

公开(公告)日：2010-04-06

申请号：US11458494

申请日：2006-07-19

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  John E. Florkey ,  Robert M. Rassel ,  Kunal Vaed

IPC分类号： H01L21/20

CPC分类号： H01L27/0802 ,  H01L21/26513 ,  H01L28/20

摘要： A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.

摘要翻译： 含多晶硅的电阻器包括：（1）选自硼和二氟化硼的p掺杂剂; 和（2）选自砷和磷的n掺杂剂。 p掺杂剂和n掺杂剂中的每一个掺杂剂的掺杂剂浓度从每立方厘米约1e18至约1e21掺杂剂原子。 用于形成多晶硅电阻器的方法使用相对于每平方厘米约1e14至约1e16掺杂剂离子的注入剂量。 p掺杂剂和n掺杂剂可以同时或顺序地提供。 对于具有约100至约5000欧姆/平方的薄层电阻的多晶硅电阻器，该方法提供某些多晶硅电阻器的薄层电阻百分比标准偏差小于约1.5％。

公开(公告)号：US20080157382A1

公开(公告)日：2008-07-03

申请号：US11617202

申请日：2006-12-28

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Anthony K. Stamper ,  Richard P. Volant

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Anthony K. Stamper ,  Richard P. Volant

IPC分类号： H01L23/48

CPC分类号： H01L23/53223 ,  H01L23/53228 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/48724 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05552

摘要： Direct termination of a wiring metal in a semiconductor device. Direct termination of an AlCu stack or an AlCu layer is made with an underlying Cu wiring level. The AlCu stack or AlCu layer covers all of the Cu wiring level such that it has a border that extends beyond all of the wiring to prevent exposure from occurring.

摘要翻译： 直接终止半导体器件中的布线金属。 AlCu堆叠或AlCu层的直接终止是用下面的铜布线层进行的。 AlCu堆叠或AlCu层覆盖所有Cu布线级别，使得其具有延伸超出所有布线的边界，以防止发生曝光。

公开(公告)号：US20080158771A1

公开(公告)日：2008-07-03

申请号：US11616955

申请日：2006-12-28

申请人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

发明人： Anil K. Chinthakindi ,  Douglas D. Coolbaugh ,  Timothy J. Dalton ,  Ebenezer E. Eshun ,  Jeffrey P. Gambino ,  Anthony K. Stamper ,  Richard P. Volant

IPC分类号： H01G4/30 ,  H01G9/00

CPC分类号： H01G4/33 ,  H01G4/005 ,  H01L23/5223 ,  H01L28/90 ,  H01L2924/0002 ,  Y10T29/417 ,  H01L2924/00

摘要： A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.

摘要翻译： 形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括在其中形成第一平面介质层和第一金属化层; 在其顶部形成第一钝化层; 在所述第一钝化层上形成平面导电层; 在指定区域中图案化和选择性地去除导电层直到第一钝化层以形成一组导电特征; 用高强度电介质涂层构图并保形地涂覆该组导电特征和暴露的第一钝化层; 在所述第一钝化层上设置第二电介质层并且包围所述一组导电特征; 图案化和选择性地去除第二衬底的部分以形成沟道和沟槽; 执行双镶嵌工艺以在沟槽和通道中形成第二金属化层，并在高强度电介质涂层上形成上导电表面。