Systems and methods for magnetic barrier assembly

    公开(公告)号:US11917773B2

    公开(公告)日:2024-02-27

    申请号:US17539745

    申请日:2021-12-01

    Applicant: Apple Inc.

    CPC classification number: H05K5/02 G01V8/20 H01F7/02

    Abstract: An embodiment of a barrier assembly includes a housing having an aperture and a magnet at least partially disposed within the housing. A first surface of the magnet is exposed. The barrier assembly also includes a light-emitting component disposed within the aperture. Another embodiment of a barrier assembly includes a housing having a plurality of apertures formed about a perimeter of the housing. The barrier assembly also includes a magnet at least partially embedded within the housing and the magnet includes an opening formed through a center of the magnet and a plurality of light-emitting components, each light-emitting component at least partially disposed within a corresponding aperture of the plurality of apertures.

    Display Systems with Light-Emitting Diodes
    15.
    发明公开

    公开(公告)号:US20230361153A1

    公开(公告)日:2023-11-09

    申请号:US18180758

    申请日:2023-03-08

    Applicant: Apple Inc.

    Abstract: An electronic device may have one or more displays that produce images for a user. The display may include an array of light-emitting diodes. Each light-emitting diode in the array of light-emitting diodes may include a plurality of vias. The vias may be arranged in an array of rows and columns. The light-emitting diodes in the array may share a common cathode. The common cathode may include a conductive layer formed from a reflective material. The conductive layer may be formed in a grid that defines a plurality of openings for the light-emitting diodes or may be formed around the periphery of the array. The array may include light-emitting diodes of two different colors in a head-to-tail arrangement, connected in series, or that share a common cathode. The array may include light-emitting diodes of three different colors that are vertically stacked.

    Preventing artifacts due to underfill in flip chip imager assembly
    18.
    发明授权
    Preventing artifacts due to underfill in flip chip imager assembly 有权
    在倒装芯片成像器组装中防止由于底部填充物造成的伪影

    公开(公告)号:US09503622B2

    公开(公告)日:2016-11-22

    申请号:US14202256

    申请日:2014-03-10

    Applicant: Apple Inc.

    Abstract: A CMOS imager assembly may include an integrated circuit (IC) having an active-pixel image sensor that is mounted on a printed circuit board (PCB) substrate using flip chip packaging technology. The IC and the PCB may be physically and electrically connected to each other through multiple electrically conductive connectors. An underfill material (which may include an anti-reflective material) may, during assembly, be introduced around the connectors in the space between the IC and the PCB. A chemical or physical discontinuity on the integrated circuit may, during assembly, prevent the underfill material from entering an area framed by the discontinuity, which may include the pixel array of the image sensor. The discontinuity may include a dam-like structure built up on the IC, a trench-like structure created on the IC, or a low surface tension material that has been applied to the surface of the IC.

    Abstract translation: CMOS成像器组件可以包括具有使用倒装芯片封装技术安装在印刷电路板(PCB)衬底上的有源像素图像传感器的集成电路(IC)。 IC和PCB可以通过多个导电连接器物理和电连接。 在组装期间,底部填充材料(其可以包括抗反射材料)可以在IC和PCB之间的空间中的连接器周围引入。 在组装期间,集成电路上的化学或物理不连续性可以在组装期间防止底部填充材料进入由不连续构成的区域,其可以包括图像传感器的像素阵列。 不连续性可以包括在IC上构建的坝状结构,在IC上形成的沟槽状结构或已经施加到IC的表面的低表面张力材料。

    Flexible Printed Circuit With Semiconductor Strain Gauge
    19.
    发明申请
    Flexible Printed Circuit With Semiconductor Strain Gauge 审中-公开
    带半导体应变片的柔性印刷电路

    公开(公告)号:US20150296622A1

    公开(公告)日:2015-10-15

    申请号:US14250942

    申请日:2014-04-11

    Applicant: Apple Inc.

    Abstract: A semiconductor strain gauge may be incorporated into a flexible printed circuit. The semiconductor strain gauge may be mounted in an opening in the flexible printed circuit. Electrical connections such as wire bonds may couple the semiconductor strain gauge to metal traces on a flexible printed circuit substrate in the flexible printed circuit. A flexible printed circuit opening may be filled with an encapsulant that encapsulates a semiconductor strain gauge. Vias may be formed through the encapsulant to contact the semiconductor strain gauge. Metal traces that run across the surface of the substrate and the encapsulant may contact the vias to form paths to the semiconductor strain gauge. A semiconductor strain gauge may be mounted on a substrate and covered with dielectric. Metal traces in a redistribution layer in the dielectric may overlap the semiconductor strain gauge and make contact to the semiconductor strain gauge.

    Abstract translation: 半导体应变计可以并入到柔性印刷电路中。 半导体应变计可以安装在柔性印刷电路中的开口中。 诸如引线接合的电连接可以将半导体应变计耦合到柔性印刷电路中柔性印刷电路基板上的金属迹线。 柔性印刷电路开口可以填充封装半导体应变计的密封剂。 可以通过密封剂形成通孔以接触半导体应变仪。 穿过衬底表面的金属痕迹和密封剂可以接触通孔以形成到半导体应变计的路径。 半导体应变计可以安装在基板上并用电介质覆盖。 电介质中再分布层中的金属迹线可能与半导体应变计重叠,并与半导体应变计接触。

    PREVENTING ARTIFACTS DUE TO UNDERFILL IN FLIP CHIP IMAGER ASSEMBLY
    20.
    发明申请
    PREVENTING ARTIFACTS DUE TO UNDERFILL IN FLIP CHIP IMAGER ASSEMBLY 有权
    防止因飞溅芯片成像器件组装而造成的故障

    公开(公告)号:US20150256725A1

    公开(公告)日:2015-09-10

    申请号:US14202256

    申请日:2014-03-10

    Applicant: Apple Inc.

    Abstract: A CMOS imager assembly may include an integrated circuit (IC) having an active-pixel image sensor that is mounted on a printed circuit board (PCB) substrate using flip chip packaging technology. The IC and the PCB may be physically and electrically connected to each other through multiple electrically conductive connectors. An underfill material (which may include an anti-reflective material) may, during assembly, be introduced around the connectors in the space between the IC and the PCB. A chemical or physical discontinuity on the integrated circuit may, during assembly, prevent the underfill material from entering an area framed by the discontinuity, which may include the pixel array of the image sensor. The discontinuity may include a dam-like structure built up on the IC, a trench-like structure created on the IC, or a low surface tension material that has been applied to the surface of the IC.

    Abstract translation: CMOS成像器组件可以包括具有使用倒装芯片封装技术安装在印刷电路板(PCB)衬底上的有源像素图像传感器的集成电路(IC)。 IC和PCB可以通过多个导电连接器物理和电连接。 在组装期间,底部填充材料(其可以包括抗反射材料)可以在IC和PCB之间的空间中的连接器周围引入。 在组装期间,集成电路上的化学或物理不连续性可以在组装期间防止底部填充材料进入由不连续构成的区域,其可以包括图像传感器的像素阵列。 不连续性可以包括在IC上构建的坝状结构,在IC上形成的沟槽状结构或已经施加到IC的表面的低表面张力材料。

Patent Agency Ranking