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    INTEGRATED CIRCUIT HAVING TSVS INCLUDING HILLOCK SUPPRESSION
    11.
    发明申请
    INTEGRATED CIRCUIT HAVING TSVS INCLUDING HILLOCK SUPPRESSION 有权
    具有TSVS的集成电路，包括HILLOCK抑制

    公开(公告)号：US20110227227A1

    公开(公告)日：2011-09-22

    申请号：US12726057

    申请日：2010-03-17

    申请人： Jeffrey Alan West

    发明人： Jeffrey Alan West

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L21/76898 ,  H01L2224/13 ,  H01L2924/1305 ,  H01L2924/1461 ,  H01L2924/00

    摘要： A method for fabricating integrated circuit (ICs) having through substrate vias (TSVs) includes forming active circuit elements on a semiconductor wafer and then forming a plurality of embedded vias through the top side of the wafer. A metal filler layer including a filler metal is deposited to fill the embedded vias. Chemical mechanical polishing (CMP) then forms a plurality of embedded TSVs that have polished top TSV surfaces having exposed filler metal. An electrically conductive hillock suppression structure is formed by forming a silicon or germanium doped region, or a silicide or germanicide at the polished top TSV surface or by forming a metal layer on the polished top TSV surface having a composition different from the filler metal. A dielectric layer is deposited on the semiconductor wafer including over the hillock suppression structure. The dielectric layer is removed over the polished top TSV surface to allow metal contact thereto.

    摘要翻译： 通过衬底通孔（TSV）制造集成电路（IC）的方法包括在半导体晶片上形成有源电路元件，然后通过晶片的顶侧形成多个嵌入的通孔。 包括填充金属的金属填充层被沉积以填充嵌入的通孔。 然后，化学机械抛光（CMP）形成具有抛光的具有暴露的填充金属的顶部TSV表面的多个嵌入式TSV。 通过在抛光的顶部TSV表面上形成硅或锗掺杂区域或硅化物或锗化硅，或者通过在具有不同于填充金属的组成的抛光顶部TSV表面上形成金属层来形成导电小丘抑制结构。 包括在小丘抑制结构上的半导体晶片上沉积介电层。 在抛光的顶部TSV表面上去除电介质层，以允许金属与其接触。

    Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies
    12.
    发明授权
    Laser-assisted cleaving of a reconstituted wafer for stacked die assemblies 有权
    用于堆叠模具组件的复原晶片的激光辅助切割

    公开(公告)号：US08575758B2

    公开(公告)日：2013-11-05

    申请号：US13197856

    申请日：2011-08-04

    申请人： Jeffrey Alan West ,  Margaret Simmons-Matthews ,  Raymundo M. Camenforte

    发明人： Jeffrey Alan West ,  Margaret Simmons-Matthews ,  Raymundo M. Camenforte

    IPC分类号： H01L23/498

    CPC分类号： H01L21/78 ,  H01L21/563 ,  H01L21/568 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1461 ,  H01L2924/00

    摘要： A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.

    摘要翻译： 一种形成堆叠管芯器件的方法包括将第一半导体管芯附着到晶片上以形成重构的晶片，然后将第二半导体管芯接合到第一半导体管芯上，以在晶片上形成多个单独堆叠的管芯器件。 支撑带附接到第二半导体管芯的底部。 切割胶带附着在晶片上。 在将切割带安装到预定的切割通道之前或之后，将该晶片激光照射，该切割线与第一半导体管芯之间的间隙对准，以在期望的切割通道机械地削弱晶片，但不切割穿过晶片。 将切割带拉动以将晶片切割成多个单个部分，以通过切割带形成附接到单个晶片部分的多个单独堆叠的裸片器件。 在切割之前移除支撑带。

    Integrated circuit having TSVS including hillock suppression
    14.
    发明授权
    Integrated circuit having TSVS including hillock suppression 有权
    具有TSVS的集成电路，包括小丘抑制

    公开(公告)号：US08227839B2

    公开(公告)日：2012-07-24

    申请号：US12726057

    申请日：2010-03-17

    申请人： Jeffrey Alan West

    发明人： Jeffrey Alan West

    IPC分类号： H01L23/48 ,  H01L29/40

    CPC分类号： H01L21/76898 ,  H01L2224/13 ,  H01L2924/1305 ,  H01L2924/1461 ,  H01L2924/00

    摘要： A method for fabricating integrated circuit (ICs) having through substrate vias (TSVs) includes forming active circuit elements on a semiconductor wafer and then forming a plurality of embedded vias through the top side of the wafer. A metal filler layer including a filler metal is deposited to fill the embedded vias. Chemical mechanical polishing (CMP) then forms a plurality of embedded TSVs that have polished top TSV surfaces having exposed filler metal. An electrically conductive hillock suppression structure is formed by forming a silicon or germanium doped region, or a silicide or germanicide at the polished top TSV surface or by forming a metal layer on the polished top TSV surface having a composition different from the filler metal. A dielectric layer is deposited on the semiconductor wafer including over the hillock suppression structure. The dielectric layer is removed over the polished top TSV surface to allow metal contact thereto.

    摘要翻译： 通过衬底通孔（TSV）制造集成电路（IC）的方法包括在半导体晶片上形成有源电路元件，然后通过晶片的顶侧形成多个嵌入的通孔。 包括填充金属的金属填充层被沉积以填充嵌入的通孔。 然后，化学机械抛光（CMP）形成具有抛光的具有暴露的填充金属的顶部TSV表面的多个嵌入式TSV。 通过在抛光的顶部TSV表面上形成硅或锗掺杂区域或硅化物或锗化硅，或者通过在具有不同于填充金属的组成的抛光顶部TSV表面上形成金属层来形成导电小丘抑制结构。 包括在小丘抑制结构上的半导体晶片上沉积介电层。 在抛光的顶部TSV表面上去除电介质层，以允许金属与其接触。