公开(公告)号：US10468399B2

公开(公告)日：2019-11-05

申请号：US14673928

申请日：2015-03-31

Applicant: Cree, Inc.

Inventor： Saurabh Goel ,  Alexander Komposch ,  Cynthia Blair ,  Cristian Gozzi

IPC: H01L23/495 ,  H01L25/00 ,  H01L23/66 ,  H01L23/538 ,  H01L23/36 ,  H01L25/065

Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces, a circuit board attached to the first main surface of the single metal flange, the circuit board having a plurality of openings which expose different regions of the first main surface of the single metal flange, and a plurality of semiconductor dies each of which is disposed in one of the openings in the circuit board and attached to the first main surface of the single metal flange. The circuit board includes a plurality of metal traces for electrically interconnecting the semiconductor dies to form a circuit. A corresponding method of manufacturing is also provided.

公开(公告)号：US11581859B2

公开(公告)日：2023-02-14

申请号：US16913783

申请日：2020-06-26

Applicant: Cree, Inc.

Inventor： Alexander Komposch ,  Qianli Mu ,  Kun Wang ,  Eng Wah Woo

IPC: H03F3/187 ,  H03F3/195 ,  H03F1/56 ,  H03F3/24

Abstract: A radio frequency (RF) transistor amplifier package includes a submount, and first and second leads extending from a first side of the submount. The first and second leads are configured to provide RF signal connections to one or more transistor dies on a surface of the submount. At least one rivet is attached to the surface of the submount between the first and second leads on the first side. One or more corners of the first side of the submount may be free of rivets. Related devices and associated RF leads and non-RF leads are also discussed.

公开(公告)号：US11424177B2

公开(公告)日：2022-08-23

申请号：US16868639

申请日：2020-05-07

Applicant: Cree, Inc.

Inventor： Mitch Flowers ,  Erwin Cohen ,  Alexander Komposch

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: A package includes an integrated circuit that includes at least one active area and at least one secondary device area, a support configured to support the integrated circuit, and a die attach material. The integrated circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.

公开(公告)号：US11257740B2

公开(公告)日：2022-02-22

申请号：US16797290

申请日：2020-02-21

Applicant: Cree, Inc.

Inventor： Alexander Komposch ,  Simon Ward ,  Madhu Chidurala

IPC: H01L23/498 ,  H01L23/66

Abstract: A device includes: a surface mount device carrier configured to be mounted to a metal submount of a transistor package, said surface mount device carrier includes an insulating substrate includes a top surface and a bottom surface and a first pad and a second pad arranged on a top surface of said surface mount device carrier; at least one surface mount device includes a first terminal and a second terminal, said first terminal of said surface mount device mounted to said first pad and said second terminal mounted to said second pad; and at least one of the first terminal and the second terminal being configured to be isolated from the metal submount by said insulating substrate, where at least one of the first pad and the second pad are configured as wire bond pads.

公开(公告)号：US20220028821A1

公开(公告)日：2022-01-27

申请号：US17494909

申请日：2021-10-06

Applicant: Cree, Inc.

Inventor： Alexander Komposch ,  Kevin Schneider ,  Scott Sheppard

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

公开(公告)号：US20210376807A1

公开(公告)日：2021-12-02

申请号：US16888957

申请日：2020-06-01

Applicant: Cree, Inc.

Inventor： Kwangmo Chris Lim ,  Basim Noori ,  Qianli Mu ,  Marvin Marbell ,  Scott Sheppard ,  Alexander Komposch

IPC: H03F3/72 ,  H03F1/56 ,  H01Q1/52 ,  H03F3/21 ,  H03F3/19 ,  H03H2/00

Abstract: RF transistor amplifiers include an RF transistor amplifier die having a semiconductor layer structure, a coupling element on an upper surface of the semiconductor layer structure, and an interconnect structure on an upper surface of the coupling element so that the RF transistor amplifier die and the interconnect structure are in a stacked arrangement. The coupling element includes a first shielded transmission line structure.

公开(公告)号：US11152325B2

公开(公告)日：2021-10-19

申请号：US16548241

申请日：2019-08-22

Applicant: Cree, Inc.

Inventor： Alexander Komposch ,  Kevin Schneider ,  Scott Sheppard

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

公开(公告)号：US20200373270A1

公开(公告)日：2020-11-26

申请号：US16421824

申请日：2019-05-24

Applicant: Cree, Inc.

Inventor： Sung Chul Joo ,  Alexander Komposch ,  Brian William Condie ,  Benjamin Law ,  Jae Hyung Jeremiah Park

IPC: H01L23/00

Abstract: A semiconductor device package includes a substrate, a silicon (Si) or silicon carbide (SiC) semiconductor die, and a metal layer on a surface of the semiconductor die. The metal layer includes a bonding surface that is attached to a surface of the substrate by a die attach material. The bonding surface includes opposing edges that extend along a perimeter of the semiconductor die, and one or more non-orthogonal corners that are configured to reduce stress at an interface between the bonding surface and the die attach material. Related devices and fabrication methods are also discussed.

公开(公告)号：US12080660B2

公开(公告)日：2024-09-03

申请号：US17228978

申请日：2021-04-13

Applicant: CREE, INC.

Inventor： Xikun Zhang ,  Dejiang Chang ,  Bill Agar ,  Michael Lefevre ,  Alexander Komposch

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L25/00 ,  H01L25/07 ,  H01L29/16

CPC classification number: H01L23/66 ,  H01L23/49503 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L24/95 ,  H01L25/072 ,  H01L25/50 ,  H01L29/16 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83121 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83855 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/29101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/29144 ,  H01L2924/0105 ,  H01L2224/29139 ,  H01L2924/0105 ,  H01L2224/29147 ,  H01L2924/0105 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012

Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.

公开(公告)号：US11935879B2

公开(公告)日：2024-03-19

申请号：US17342925

申请日：2021-06-09

Applicant: CREE, INC

Inventor： Eng Wah Woo ,  Samantha Cheang ,  Kok Meng Kam ,  Marvin Mabell ,  Haedong Jang ,  Alexander Komposch

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/047 ,  H01L23/66

CPC classification number: H01L25/165 ,  H01L21/4817 ,  H01L23/047 ,  H01L23/66 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2223/6672 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/73265 ,  H01L2924/1033 ,  H01L2924/1205 ,  H01L2924/1207 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/1421

Abstract: A transistor package that includes a metal submount; a transistor die mounted on said metal submount; a surface mount IPD component that includes a dielectric substrate; and the dielectric substrate mounted on said metal submount. Additionally, the dielectric substrate includes one of the following: an irregular shape, a non-square shape, and a nonrectangular shape.