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公开(公告)号：US08941231B2
公开(公告)日：2015-01-27
申请号：US13938324
申请日：2013-07-10
Inventor： Young Rak Park , Sang Choon Ko , Byoung-Gue Min , Jong-Won Lim , Hokyun Ahn , Sung-Bum Bae , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L23/12 , H01L29/66 , H01L23/522 , H01L23/532 , H01L23/66
CPC classification number: H01L29/66477 , H01L23/5225 , H01L23/5228 , H01L23/5329 , H01L23/66 , H01L2223/6627 , H01L2223/6683 , H01L2924/0002 , H01L2924/00
Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.
Abstract translation: 提供一种电子芯片及其制造方法。 半导体芯片可以包括衬底，集成在衬底上的有源器件，覆盖所提供的有源器件的结构的下层间绝缘层，设置在下层间绝缘层上的无源器件，覆盖所得到的上层间绝缘层 设置有无源器件的结构，以及设置在上层间绝缘层上的接地电极。 上层间绝缘层可以由其介电常数可能高于下层间绝缘层的材料的材料形成。
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公开(公告)号：US11955961B2
公开(公告)日：2024-04-09
申请号：US17879047
申请日：2022-08-02
Inventor： Hong Gu Ji , Dong Min Kang , Byoung-Gue Min , Jongmin Lee , Kyu Jun Cho
IPC: H03K3/00 , H03K17/687 , H03K17/693
CPC classification number: H03K17/687
Abstract: Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.
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公开(公告)号：US11817826B2
公开(公告)日：2023-11-14
申请号：US17886061
申请日：2022-08-11
Inventor： Woojin Chang , Dong Min Kang , Byoung-Gue Min , Jong Yul Park , Jongmin Lee , Yoo Jin Jang , Kyu Jun Cho , Hong Gu Ji
Abstract: Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.
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公开(公告)号：US10134854B2
公开(公告)日：2018-11-20
申请号：US15248676
申请日：2016-08-26
Inventor： Ho Kyun Ahn , Dong Min Kang , Yong-Hwan Kwon , Dong-Young Kim , Seong Il Kim , Hae Cheon Kim , Eun Soo Nam , Jae Won Do , Byoung-Gue Min , Hyung Sup Yoon , Sang-Heung Lee , Jong Min Lee , Jong-Won Lim , Hyun Wook Jung , Kyu Jun Cho
IPC: H01L29/40 , H01L29/20 , H01L29/205 , H01L29/778 , H01L29/66
Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
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公开(公告)号：US09634112B2
公开(公告)日：2017-04-25
申请号：US14633984
申请日：2015-02-27
Inventor： Hyung Sup Yoon , Byoung-Gue Min , Jong-Won Lim , Hokyun Ahn , Seong-Il Kim , Sang Heung Lee , Dong Min Kang , Chull Won Ju , Jae Kyoung Mun
IPC: H01L29/66 , H01L29/778 , H01L29/40 , H01L29/423 , H01L29/20 , H01L21/02 , H01L21/28 , H01L21/311 , H01L29/201 , H01L29/205 , H01L21/285
CPC classification number: H01L29/66462 , H01L21/02118 , H01L21/0217 , H01L21/02178 , H01L21/0254 , H01L21/28264 , H01L21/28593 , H01L21/31111 , H01L21/31144 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/404 , H01L29/42316 , H01L29/42376 , H01L29/778 , H01L29/7786
Abstract: A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode.
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Patent Agency Ranking
公开(公告)号：US09490214B2
公开(公告)日：2016-11-08
申请号：US14845435
申请日：2015-09-04
Inventor： Byoung-Gue Min , Sang Choon Ko , Jong-Won Lim , Hokyun Ahn , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L23/535 , H01L21/768 , H01L21/02 , H01L23/48 , H01L21/28
CPC classification number: H01L23/535 , H01L21/02365 , H01L21/28 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
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公开(公告)号：US09159612B2
公开(公告)日：2015-10-13
申请号：US14021269
申请日：2013-09-09
Inventor： Byoung-Gue Min , Sang Choon Ko , Jong-Won Lim , Hokyun Ahn , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L21/768 , H01L21/02 , H01L23/48 , H01L21/28
CPC classification number: H01L23/535 , H01L21/02365 , H01L21/28 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
Abstract translation: 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。
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公开(公告)号：US20140167070A1
公开(公告)日：2014-06-19
申请号：US13938324
申请日：2013-07-10
Inventor： Young Rak PARK , Sang Choon Ko , Byoung-Gue Min , Jong-Won Lim , Hokyun Ahn , Sung-Bum Bae , Jae Kyoung Mun , Eun Soo Nam
CPC classification number: H01L29/66477 , H01L23/5225 , H01L23/5228 , H01L23/5329 , H01L23/66 , H01L2223/6627 , H01L2223/6683 , H01L2924/0002 , H01L2924/00
Abstract: Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.
Abstract translation: 提供一种电子芯片及其制造方法。 半导体芯片可以包括衬底，集成在衬底上的有源器件，覆盖所提供的有源器件的结构的下层间绝缘层，设置在下层间绝缘层上的无源器件，覆盖所得到的上层间绝缘层 设置有无源器件的结构，以及设置在上层间绝缘层上的接地电极。 上层间绝缘层可以由其介电常数可能高于下层间绝缘层的材料的材料形成。
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公开(公告)号：US20140159049A1
公开(公告)日：2014-06-12
申请号：US13905213
申请日：2013-05-30
Inventor： Sang Choon KO , Jae Kyoung Mun , Byoung-Gue Min , Young Rak Park , Hokyun Ahn , Jeong-Jin Kim , Eun Soo Nam
IPC: H01L29/66 , H01L29/808
CPC classification number: H01L29/808 , H01L21/76898 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/432 , H01L29/454 , H01L29/66462 , H01L29/7786
Abstract: A method of manufacturing a semiconductor device includes forming devices including source, drain and gate electrodes on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked, etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode, conformally forming a ground interconnection on the back surface of the substrate having the via-hole, forming a protecting layer on the front surface of the substrate, and cutting the substrate to separate the devices from each other.
Abstract translation: 一种制造半导体器件的方法包括在包括体硅，掩埋氧化物层，活性硅，氮化镓层和铝 - 氮化镓层的衬底的前表面上形成包括源极，漏极和栅电极的器件 依次堆叠，蚀刻基板的背面以形成穿透基板的通孔并暴露源电极的底表面，在具有通孔的基板的背面上共形形成接地互连，形成保护 层，并且切割基板以将装置彼此分离。
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20.发明申请IMPEDANCE MATCHING CIRCUIT, POWER AMPLIFIER AND MANUFACTURING METHOD FOR VARIABLE CAPACITOR 审中-公开阻抗匹配电路，功率放大器和可变电容器的制造方法公开(公告)号：US20130207730A1
公开(公告)日：2013-08-15
申请号：US13743667
申请日：2013-01-17
Inventor： Jongmin LEE , Byoung-Gue Min , Seong-Il Kim , Hyung Sup Yoon , Jae Kyoung Mun , Eun Soo Nam
CPC classification number: H01L21/8222 , H01G7/00 , H01L27/0647 , H01L27/0658 , H01L29/93 , H03F1/565 , H03F3/21 , H03F2200/36 , H03F2200/378 , H03F2200/387 , H03F2200/391 , H03H7/38 , Y10T29/43
Abstract: Disclosed is an impedance matching circuit capable of wideband matching. The impedance matching circuit includes: a first variable inductor unit of which one end is connected to the first node and an inductance value varies; a second inductor unit connected between the first node and a second node and having a variable inductance value; a first variable capacitor unit of which one end is connected to the first node and a capacitance value varies; and a second variable capacitor unit of which one end is connected to the second node and a capacitance value varies, and the other end of the first variable capacitor unit and the other end of the second variable capacitor unit are connected to a ground voltage terminal to perform the impedance matching between a circuit connected to the other end of the first variable inductor unit and a circuit connected to the second node.
Abstract translation: 公开了能够进行宽带匹配的阻抗匹配电路。 阻抗匹配电路包括：第一可变电感器单元，其一端连接到第一节点，电感值变化; 连接在第一节点和第二节点之间并具有可变电感值的第二电感器单元; 第一可变电容器单元，其一端连接到第一节点，电容值变化; 以及第二可变电容器单元，其一端连接到第二节点并且电容值变化，并且第一可变电容器单元的另一端和第二可变电容器单元的另一端连接到接地电压端子 执行连接到第一可变电感器单元的另一端的电路与连接到第二节点的电路之间的阻抗匹配。
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