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公开(公告)号：US09948311B1
公开(公告)日：2018-04-17
申请号：US15420764
申请日：2017-01-31
Applicant: Finisar Corporation
Inventor： The'Linh Nguyen
CPC classification number: H03L7/085 , H03L7/0807 , H04L7/0004 , H04L7/033 , H04L7/0334 , H04L25/03
Abstract: A decision-directed phase detector (DDPD) to compare an input signal including clock and data components with a reference signal set to a clock crossover value, and generate a first compared output signal designating a transition of the input signal through the clock crossover value. The DDPD may also receive the first compared output signal and generate a phase adjustment signal, and compare the input signal with the reference signal set to a positive offset clock crossover value of the clock crossover value offset by a positive offset value, and generate a positive offset compared output signal designating a transition of the input signal through the positive offset clock crossover value. The DDPD may further generate a valid transition signal to route the phase adjustment signal to a clock generation circuit when the positive offset compared output signal transitions over a clock period.
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公开(公告)号：US09467153B2
公开(公告)日：2016-10-11
申请号：US14691558
申请日：2015-04-20
Applicant: FINISAR CORPORATION
Inventor： The'Linh Nguyen , Steven Gregory Troyer , Daniel K. Case
CPC classification number: H03L7/091 , H03L7/0805 , H03L7/0807 , H03L7/093 , H04L7/0016 , H04L7/033
Abstract: In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.
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公开(公告)号：US09103725B2
公开(公告)日：2015-08-11
申请号：US13761328
申请日：2013-02-07
Applicant: FINISAR CORPORATION
Inventor： Henry Meyer Daghighian , The'Linh Nguyen , Chris Kocot
CPC classification number: G01J1/44 , G01R29/08 , G01R31/001 , G02B6/4277 , H04B15/00 , H04B15/04
Abstract: A method of compensating for electromagnetic radiation. The method may include measuring electromagnetic radiation emanating from circuitry at a first frequency and adjusting at least one of the electrical settings of the circuitry based on the measurement of the electromagnetic radiation to reduce the electromagnetic radiation at the first frequency emanating from the circuitry.
Abstract translation: 补偿电磁辐射的方法。 该方法可以包括测量从第一频率的电路发出的电磁辐射，并且基于电磁辐射的测量来调整电路的电气设置中的至少一个，以减少从电路发出的第一频率处的电磁辐射。
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公开(公告)号：US20150139252A1
公开(公告)日：2015-05-21
申请号：US14542251
申请日：2014-11-14
Applicant: FINISAR CORPORATION
Inventor： The'Linh Nguyen , Daniel K. Case
CPC classification number: H04L7/0331 , H03L7/0807 , H03M9/00 , H04J3/047 , H04J3/0635 , H04L7/0041 , H04L7/033 , H04L25/14
Abstract: A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.
Abstract translation: 串行器电路可以包括恢复电路，调整电路和多路复用器电路。 恢复电路可以被配置为以第一频率接收第一数据信号，以使用第一数据信号产生第一频率的第一时钟信号，并且基于第一时钟信号重新计算第一数据信号，以产生重定时 第一数据信号。 调整电路可以被配置为接收第二数据信号并基于第一时钟信号重新计时第二数据信号，以产生重新定时的第二数据信号。 复用器电路可以被配置为对重新定时的第一数据信号和重定时的第二数据信号进行复用。
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Patent Agency Ranking
公开(公告)号：US20140219665A1
公开(公告)日：2014-08-07
申请号：US13916406
申请日：2013-06-12
Applicant: Finisar Corporation
Inventor： The'Linh Nguyen , Henry M. Daghighian
IPC: H04L25/03 , H04B10/564
CPC classification number: H04B10/564 , H04B10/2504 , H04B10/2575 , H04L25/03847
Abstract: In one example embodiment, a transmitter module includes a header electrically coupled to a chassis ground. First and second input nodes are configured to receive a differential data signal. A buffer stage has a first node coupled to the first input node and a second node coupled to the second input node. An amplifier stage has a fifth node coupled to a third node of the buffer stage and a sixth node coupled to a signal ground that is not coupled to the chassis ground. An optical transmitter has an eighth node coupled to a seventh node of the amplifier stage and a ninth node configured to be coupled to a voltage source. A bias circuit is configured to couple a fourth node of the buffer stage to a bias current source.
Abstract translation: 在一个示例实施例中，发射机模块包括电耦合到底盘接地的接头。 第一和第二输入节点被配置为接收差分数据信号。 缓冲器级具有耦合到第一输入节点的第一节点和耦合到第二输入节点的第二节点。 放大器级具有耦合到缓冲级的第三节点的第五节点和耦合到未耦合到机架接地的信号地的第六节点。 光发射机具有耦合到放大器级的第七节点的第八节点和被配置为耦合到电压源的第九节点。 偏置电路被配置为将缓冲器级的第四节点耦合到偏置电流源。
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公开(公告)号：US10129016B2
公开(公告)日：2018-11-13
申请号：US14542251
申请日：2014-11-14
Applicant: FINISAR CORPORATION
Inventor： The'Linh Nguyen , Daniel K. Case
Abstract: A serializer circuit may include a recovery circuit, an adjusting circuit, and a multiplexer circuit. The recovery circuit may be configured to receive a first data signal at a first frequency, to generate a first clock signal at the first frequency using the first data signal, and to retime the first data signal based on the first clock signal to generate a retimed first data signal. The adjusting circuit may be configured to receive a second data signal and retime the second data signal based on the first clock signal to generate a retimed second data signal. The multiplexer circuit may be configured to multiplex the retimed first data signal and the retimed second data signal.
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公开(公告)号：US09379709B2
公开(公告)日：2016-06-28
申请号：US14738472
申请日：2015-06-12
Applicant: FINISAR CORPORATION
Inventor： The'Linh Nguyen
IPC: H03K19/0185 , H03K19/094 , H03K19/018 , H03K3/017 , H03K19/0175
CPC classification number: H03K19/018528 , H03K3/017 , H03K5/1565 , H03K19/017509 , H03K19/01806 , H03K19/018514
Abstract: A circuit may include an input terminal configured to receive an input signal with a first voltage swing and an output terminal. The circuit may also include a first transistor, a second transistor, a third transistor, and a control circuit. The control circuit may be coupled to the input terminal, a gate terminal of the first transistor, and a gate terminal of the second transistor. The control circuit may be configured to adjust voltages provided to the gate terminals based on the input signal such that the first transistor conducts in response to the input signal being at a first logical level and the second transistor conducts in response to the input signal being at a second logical level to generate an output signal output on the output terminal. The second voltage swing of the output signal may be different from the first voltage swing of the input signal.
Abstract translation: 电路可以包括被配置为接收具有第一电压摆幅和输出端子的输入信号的输入端子。 电路还可以包括第一晶体管，第二晶体管，第三晶体管和控制电路。 控制电路可以耦合到输入端子，第一晶体管的栅极端子和第二晶体管的栅极端子。 控制电路可以被配置为基于输入信号来调整提供给栅极端子的电压，使得第一晶体管响应于第一逻辑电平而导通，并且第二晶体管响应于输入信号在 第二逻辑电平以在输出端子上产生输出信号。 输出信号的第二电压摆幅可以与输入信号的第一电压摆幅不同。
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公开(公告)号：US20150155949A1
公开(公告)日：2015-06-04
申请号：US14612035
申请日：2015-02-02
Applicant: FINISAR CORPORATION
Inventor： The'Linh Nguyen , Henry M. Daghighian
IPC: H04B10/564 , H04B10/2575 , H04B10/25
CPC classification number: H04B10/564 , H04B10/2504 , H04B10/2575 , H04L25/03847
Abstract: In one example embodiment, a transmitter module includes a header electrically coupled to a chassis ground. First and second input nodes are configured to receive a differential data signal. A buffer stage has a first node coupled to the first input node and a second node coupled to the second input node. An amplifier stage has a fifth node coupled to a third node of the buffer stage and a sixth node coupled to a signal ground that is not coupled to the chassis ground. An optical transmitter has an eighth node coupled to a seventh node of the amplifier stage and a ninth node configured to be coupled to a voltage source. A bias circuit is configured to couple a fourth node of the buffer stage to a bias current source.
Abstract translation: 在一个示例实施例中，发射机模块包括电耦合到底盘接地的接头。 第一和第二输入节点被配置为接收差分数据信号。 缓冲器级具有耦合到第一输入节点的第一节点和耦合到第二输入节点的第二节点。 放大器级具有耦合到缓冲级的第三节点的第五节点和耦合到未耦合到机架接地的信号地的第六节点。 光发射机具有耦合到放大器级的第七节点的第八节点和被配置为耦合到电压源的第九节点。 偏置电路被配置为将缓冲器级的第四节点耦合到偏置电流源。
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19.发明申请公开(公告)号：US20130200930A1
公开(公告)日：2013-08-08
申请号：US13761036
申请日：2013-02-06
Applicant: FINISAR CORPORATION
Inventor： Henry M. Daghighian , Luke M. Ekkizogloy , The'Linh Nguyen , Christopher Kocot , James Prettyleaf
IPC: H03K3/013
Abstract: An example embodiment includes a fiber optic integrated circuit (IC). The fiber optic IC includes an integrated power supply. The integrated power supply includes a filter, an active switch, and a pulse width modulator (“PWM”). The filter is configured to convert a signal to an output signal of the integrated power supply. The active switch is configured to control introduction of the signal to the filter. The PWM is configured to generate a PWM output signal that triggers the active switch.
Abstract translation: 示例实施例包括光纤集成电路（IC）。 光纤IC包括集成电源。 集成电源包括滤波器，有源开关和脉宽调制器（“PWM”）。 滤波器被配置为将信号转换成集成电源的输出信号。 有源开关被配置为控制信号到滤波器的引入。 PWM被配置为产生触发有源开关的PWM输出信号。
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