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    CONSTRAINED NANOSECOND LASER ANNEAL OF METAL INTERCONNECT STRUCTURES
    11.
    发明申请
    CONSTRAINED NANOSECOND LASER ANNEAL OF METAL INTERCONNECT STRUCTURES 有权
    金属互连结构的约束纳米激光雷达

    公开(公告)号：US20160086849A1

    公开(公告)日：2016-03-24

    申请号：US14490792

    申请日：2014-09-19

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Oleg Gluschenkov ,  Siddarth A. Krishnan ,  Joyeeta Nag ,  Andrew H. Simon ,  Shishir Ray

    IPC: H01L21/768

    CPC classification number: H01L21/76894 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/00

    Abstract: In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material.

    Abstract translation: 密封铜线的原位熔融和结晶可以通过激光退火进行纳秒的持续时间。 选择激光照射的强度，使得熔融铜浸润互连界面，从而形成增加电子的镜面散射的界面结合装置。 纳秒级温度淬火保持形成的界面结合。 同时，密封铜互连的快速结晶过程平均导致大的铜晶粒，通常大于80nm的横向尺寸。 退火过程的典型持续时间为约10秒至约100秒的纳秒。 尽管由于超短时间的高退火温度，层间低k介电材料没有劣化，从而防止原子在电介质材料内的集体运动。

    Hybrid graphene-metal interconnect structures
    12.
    发明授权
    Hybrid graphene-metal interconnect structures 有权
    混合石墨烯 - 金属互连结构

    公开(公告)号：US09257391B2

    公开(公告)日：2016-02-09

    申请号：US13873356

    申请日：2013-04-30

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  Ronald G. Filippi ,  Naftali E. Lustig ,  Andrew H. Simon

    IPC: H01L21/4763 ,  H01L21/44 ,  H01L23/532 ,  H01L23/528 ,  B82Y40/00 ,  B82Y30/00 ,  H01L21/768

    CPC classification number: H01L23/53276 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  Y10S977/734 ,  Y10S977/842 ,  Y10S977/932 ,  H01L2924/00

    Abstract: Hybrid metal-graphene interconnect structures and methods of forming the same. The structure may include a first end metal, a second end metal, a conductive line including one or more graphene portions extending from the first end metal to the second end metal, and one or more line barrier layers partially surrounding each of the one or more graphene portions. The conductive line may further include one or more intermediate metals separating each of the one or more graphene portions. Methods of forming said interconnect structures may include forming a plurality of metals including a first end metal and a second end metal in a dielectric layer, forming one or more line trenches between each of the plurality of metals, forming a line barrier layer in each of the one or more line trenches, and filling the one or more line trenches with graphene.

    Abstract translation: 混合金属 - 石墨烯互连结构及其形成方法。 该结构可以包括第一端金属，第二端金属，包括从第一端金属延伸到第二端金属的一个或多个石墨烯部分的导电线，以及一个或多个部分围绕一个或多个 石墨烯部分。 导电线还可以包括分离一个或多个石墨烯部分中的每一个的一个或多个中间金属。 形成所述互连结构的方法可以包括在电介质层中形成包括第一端金属和第二端金属的多种金属，在多个金属中的每一个之间形成一个或多个管线沟槽，在每一个中形成线路阻挡层 一个或多个线沟槽，并用石墨烯填充一个或多个线沟槽。

    Interconnect structure and method of forming
    15.
    发明授权
    Interconnect structure and method of forming 有权

    公开(公告)号：US10177091B2

    公开(公告)日：2019-01-08

    申请号：US15048114

    申请日：2016-02-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Andrew H. Simon ,  Chih-Chao Yang

    IPC: H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

    Abstract: Aspects of the present disclosure include a method of forming a semiconductor interconnect structure and the interconnect structure. The method includes etching an opening in a first interconnect dielectric material. The method includes performing a nitridation process that converts the surfaces of the opening into nitride residues, and forms a nitrided interconnect dielectric material surface in the opening. The method includes depositing tantalum to create a tantalum layer on the nitrided interconnect dielectric surface region. The method includes depositing copper to fill the opening and planarizing the surface of the first dielectric material.

    Detecting a void between a via and a wiring line
    16.
    发明授权
    Detecting a void between a via and a wiring line 有权

    公开(公告)号：US10103068B2

    公开(公告)日：2018-10-16

    申请号：US14743208

    申请日：2015-06-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

    IPC: H01L21/66 ,  G01R31/28

    Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

    Structure with air gap crack stop
    19.
    发明授权
    Structure with air gap crack stop 有权
    结构带气隙裂缝停止

    公开(公告)号：US09536842B2

    公开(公告)日：2017-01-03

    申请号：US14574430

    申请日：2014-12-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  Ronald G. Filippi ,  Xiao H. Liu ,  Naftali E. Lustig ,  Andrew H. Simon

    IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

    CPC classification number: H01L23/562 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a dielectric layer, and a dielectric capping layer directly on top of the dielectric layer and directly on top of the metal interconnect, the crack stop is an air gap which intersects an interface between the dielectric layer and the dielectric capping layer of each interconnect level, and forming a through substrate via through the multiple interconnect levels adjacent to, but not in direct contact with, the crack stop, the crack stop of each interconnect level is directly between the metal interconnect of each interconnect level and the through substrate via to prevent cracks caused during fabrication from propagating away from the through substrate via and damaging the metal interconnect.

    Abstract translation: 一种包括在彼此之上形成多个互连层的方法，每个层包括金属互连和嵌入在电介质层中的裂纹阻挡层，以及直接位于介电层顶部并且直接位于金属互连顶部的电介质覆盖层 裂缝停止是与每个互连层的电介质层和电介质覆盖层之间的界面相交的气隙，并且通过与裂纹停止相邻但不直接接触的多个互连层形成通孔基板通孔 每个互连级别的裂纹停止点直接位于每个互连级别的金属互连和贯通基板通孔之间，以防止制造过程中产生的裂纹从穿过基板传播并损坏金属互连。

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