公开(公告)号：US09899525B2

公开(公告)日：2018-02-20

申请号：US15592597

申请日：2017-05-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Chung-Hsun Lin ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7851 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: This disclosure relates to a fin field effect transistor including a gate structure formed on a fin. Source and drain (S/D) regions are epitaxially grown on the fin adjacent to the gate structure. The S/D regions include a diamond-shaped cross section wherein the diamond-shaped cross section includes: internal sidewalls where the fin was recessed to a reduced height, and an external top portion of the diamond-shaped cross section of the S/D regions. A contact liner is formed over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions; and contacts are formed over the contact liner and over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions.

公开(公告)号：US09825093B2

公开(公告)日：2017-11-21

申请号：US14832108

申请日：2015-08-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chung H. Lam ,  Chung-Hsun Lin ,  Darsen D. Lu ,  Philip J. Oldiges

IPC: H01L27/24 ,  H01L29/08 ,  H01L45/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L27/2436 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L45/06

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.

公开(公告)号：US09716036B2

公开(公告)日：2017-07-25

申请号：US14733398

申请日：2015-06-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L27/12

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

公开(公告)号：US09711648B1

公开(公告)日：2017-07-18

申请号：US15232164

申请日：2016-08-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Effendi Leobandung ,  Chung-Hsun Lin ,  Amlan Majumdar ,  Yanning Sun

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78603 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/66522 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: A semiconductor structure is provided that includes a channel material portion composed of a III-V compound semiconductor located on a mesa portion of a substrate. A dielectric spacer structure is located on each sidewall surface of the channel material portion and each sidewall surface of the mesa portion of the substrate. The dielectric spacer structure has a height that is greater than a height of the channel material portion. An isolation structure is located on each dielectric spacer structure, wherein a sidewall edge of the isolation structure is located between an innermost sidewall surface and an outermost sidewall surface of the dielectric spacer structure.

公开(公告)号：US20160358852A1

公开(公告)日：2016-12-08

申请号：US14733398

申请日：2015-06-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Leland Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  Adam M. Pyzyna

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/743 ,  H01L21/76895 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/1203

Abstract: An electronic device is provided. The electronic device includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, circuitry disposed on the dielectric layer that includes interconnected cells, first contact line metallization and second contact line metallization, first power metallization disposed in-plane with or above the circuitry and second power metallization disposed in a trench defined in at least the dielectric layer. The electronic device further includes insulation disposed to insulate the second power metallization from the circuitry and the first power metallization at first locations and to permit electrical communication between the second power metallization, the circuitry and the first power metallization at second locations.

Abstract translation: 提供电子设备。 电子器件包括半导体层，设置在半导体层上的电介质层，设置在电介质层上的电路，包括互连电池，第一接触线金属化和第二接触线金属化，第一电力金属化设置在电路内或电路之上 以及设置在至少所述介电层中限定的沟槽中的第二功率金属化。 电子设备还包括绝缘体，其设置成在第一位置处将第二功率金属化与电路和第一功率金属化绝缘，并且允许在第二位置处的第二功率金属化，电路和第一功率金属化之间的电通信。

公开(公告)号：US20170250285A1

公开(公告)日：2017-08-31

申请号：US15592597

申请日：2017-05-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Chung-Hsun Lin ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: This disclosure relates to a fin field effect transistor including a gate structure formed on a fin. Source and drain (S/D) regions are epitaxially grown on the fin adjacent to the gate structure. The S/D regions include a diamond-shaped cross section wherein the diamond-shaped cross section includes: internal sidewalls where the fin was recessed to a reduced height, and an external top portion of the diamond-shaped cross section of the S/D regions. A contact liner is formed over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions; and contacts are formed over the contact liner and over the internal sidewalls and the top portion of the diamond-shaped cross section of the S/D regions.

公开(公告)号：US09385027B2

公开(公告)日：2016-07-05

申请号：US14811236

申请日：2015-07-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Chung-Hsun Lin ,  HsinYu Tsai

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76816 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L22/34 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one aspect, a DSA-based method for forming a Kelvin-testable structure includes the following steps. A guide pattern is formed on a substrate which defines i) multiple pad regions of the Kelvin-testable structure and ii) a region interconnecting two of the pad regions on the substrate. A self-assembly material is deposited onto the substrate and is annealed at a temperature/duration sufficient to cause it to undergo self-assembly to form a self-assembled pattern on the substrate, wherein the self-assembly is directed by the guide pattern such that the self-assembled material in the region interconnecting the two pad regions forms multiple straight lines. A pattern of the self-assembled material is transferred to the substrate forming multiple lines in the substrate, wherein the pattern of the self-assembled material is configured such that only a given one of the lines is a continuous line between the two pad regions on the substrate.