公开(公告)号：US20190252267A1

公开(公告)日：2019-08-15

申请号：US16390232

申请日：2019-04-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Chanro Park ,  Min Gyu Sung ,  Lars Liebmann ,  Su Chen Fan ,  Brent Anderson

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/823821 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78642

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US10290549B2

公开(公告)日：2019-05-14

申请号：US15695229

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Edward Joseph Nowak ,  Nigel G. Cave ,  Lars Liebmann ,  Daniel Chanemougame ,  Andreas Knorr

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11

Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.

公开(公告)号：US10026824B1

公开(公告)日：2018-07-17

申请号：US15408540

申请日：2017-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Andre Labonte ,  Ruilong Xie ,  Lars Liebmann ,  Nigel Cave ,  Guillaume Bouche

IPC: H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L21/306 ,  H01L21/84 ,  H01L21/28 ,  H01L27/12 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L29/40 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/108 ,  H01L21/8234

Abstract: Disclosed are integrated circuit (IC) structures and formation methods. In the methods, a gate with a sacrificial gate cap and a sacrificial gate sidewall spacer is formed on a channel region. The cap and sidewall spacer are removed, creating a cavity with a lower portion between the sidewalls of the gate and adjacent metal plugs and with an upper portion above the lower portion and the gate. A first dielectric layer is deposited, forming an air-gap in the lower portion and lining the upper portion. A second dielectric layer is deposited, filling the upper portion. During formation of a gate contact opening (optionally over an active region), the second dielectric layer is removed and the first dielectric layer is anisotropically etched, thereby exposing the gate and creating a dielectric spacer with a lower air-gap segment and an upper solid segment. Metal deposited into the opening forms the gate contact.

公开(公告)号：US09941162B1

公开(公告)日：2018-04-10

申请号：US15354212

申请日：2016-11-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Lars Liebmann

IPC: H01L21/768 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/40 ,  H01L29/417 ,  H01L27/092 ,  H01L21/28 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/28247 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/785 ,  H01L2029/7858

Abstract: Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region of a field effect transistor (FET) and provide protection against shorts between the gate contact and metal plugs on source/drain regions and between the gate and source/drain contacts to the metal plugs. A gate with a dielectric cap and dielectric sidewall spacer is formed on a FET channel region. Metal plugs with additional dielectric caps are formed on the FET source/drain regions such that the dielectric sidewall spacer is between the gate and the metal plugs and between the dielectric cap and the additional dielectric caps. The dielectric cap, dielectric sidewall spacer and additional dielectric caps are different materials preselected to be selectively etchable, allowing for misalignment of a contact opening to the gate without risking exposure of any metal plugs and vice versa.

公开(公告)号：US09929157B1

公开(公告)日：2018-03-27

申请号：US15387933

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Murat Kerem Akarvardar ,  Lars Liebmann ,  Nigel Graeme Cave

IPC: H01L27/088 ,  H01L29/45 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/283 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L2029/7858

Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.

公开(公告)号：US11201152B2

公开(公告)日：2021-12-14

申请号：US15958426

申请日：2018-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Soss ,  Steven Bentley ,  Daniel Chanemougame ,  Julien Frougier ,  Bipul Paul ,  Lars Liebmann

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/51

Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

公开(公告)号：US10685874B1

公开(公告)日：2020-06-16

申请号：US16220565

申请日：2018-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hui Zang ,  Lei Sun ,  Lars Liebmann ,  Daniel Chanemougame ,  Guillaume Bouche

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.

公开(公告)号：US20190326165A1

公开(公告)日：2019-10-24

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US10411010B2

公开(公告)日：2019-09-10

申请号：US15862064

申请日：2018-01-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Murat Kerem Akarvardar ,  Lars Liebmann ,  Nigel Graeme Cave

IPC: H01L27/088 ,  H01L29/45 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092

Abstract: Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures that provide increased drive current over conventional single-fin FINFET structures. The use of such a tall single-fin FINFET provides significant area savings over a FINFET that requires multiple semiconductor fins to achieve the same amount of drive current. Furthermore, since only a single fin is used, only a single leakage path is present at the bottom of the device. Thus, the disclosed FINFET structures can be incorporated into a cell in place of multi-fin FINFETs in order to allow for cell height scaling without violating critical design rules or sacrificing performance.

公开(公告)号：US20190259670A1

公开(公告)日：2019-08-22

申请号：US15899508

申请日：2018-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei L. Zhuang ,  Balasubramanian Pranatharthiharan ,  Lars Liebmann ,  Ruilong Xie ,  Terence Hook

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: In a self-aligned fin cut process for fabricating integrated circuits, a sacrificial gate or an epitaxially-formed source/drain region is used as an etch mask in conjunction with a fin cut etch step to remove unwanted portions of the fins. The process eliminates use of a lithographically-defined etch mask to cut the fins, which enables precise and accurate alignment of the fin cut.