公开(公告)号：US20150021695A1

公开(公告)日：2015-01-22

申请号：US13944048

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Richard J. Carter ,  Andy Wei ,  Qi Zhang ,  Sruthi Muralidharan ,  Amy L. Child

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

Abstract translation: 提供了在半导体器件（例如，鳍式场效应晶体管器件）的外延连接区域中实现均匀外延（epi）生长的方法。 具体地说，提供了一种半导体器件，包括形成在衬底上的伪栅极和一组鳍状场效应晶体管（FinFET）; 形成在所述伪栅极和所述一组FinFET中的每一个上的间隔层; 以及形成在衬底中的一组凹部内的外延材料，该组凹陷在去除伪栅极之前的外延阻挡层之前形成。

公开(公告)号：US09455198B1

公开(公告)日：2016-09-27

申请号：US14676034

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Lun Zhao ,  Richard J. Carter ,  Xusheng Wu

IPC: H01L21/8234 ,  H01L21/308

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/66

Abstract: One illustrative method disclosed herein includes, among other things, removing at least one, but not all, of a plurality of first features in a first patterned mask layer so as to define a modified first patterned masking layer, wherein removed first feature(s) correspond to a location where a final isolation structure will be formed, performing an etching process though the modified first patterned masking layer to form an initial isolation trench in the substrate, and performing another etching process through the modified first patterned mask layer to thereby define a plurality of fin-formation trenches in the substrate and to extend a depth of the initial isolation trench so as to define a final isolation trench for the final isolation structure.

Abstract translation: 本文公开的一种说明性方法包括除去第一图案化掩模层中的多个第一特征中的至少一个但不是全部的，以便限定经修改的第一图案化掩模层，其中去除的第一特征 对应于将形成最终隔离结构的位置，通过经修改的第一图案化掩模层执行蚀刻工艺，以在衬底中形成初始隔离沟槽，以及通过修改的第一图案化掩模层执行另一蚀刻工艺，由此限定 在衬底中的多个翅片形成沟槽并且延伸初始隔离沟槽的深度，以便限定用于最终隔离结构的最终隔离沟槽。

公开(公告)号：US09362176B2

公开(公告)日：2016-06-07

申请号：US14319640

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhao Lun ,  Zhenyu Hu ,  Richard J. Carter

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/823481 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.

Abstract translation: 对于浅沟槽隔离和其中具有介电材料的深结构沟槽（例如，可流动的氧化物和HARP氧化物）分别使用两种不同的材料导致用于非平面半导体器件的凸起半导体结构的暴露部分的不均匀高度， 由于材料的蚀刻速率不同。 与凸起结构的暴露部分相邻的不均匀的开口不会使隔离和介电材料凹陷，填充有额外的电介质材料，以形成均匀的一层材料（电介质材料）的顶层，然后可将其均匀地凹入以露出均匀的部分 的凸起结构。

公开(公告)号：US09324841B2

公开(公告)日：2016-04-26

申请号：US14049848

申请日：2013-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Hyucksoo Yang ,  Huang Liu ,  Richard J. Carter

IPC: H01L21/20 ,  H01L21/336 ,  H01L29/76 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/8238 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.

Abstract translation: 本发明的实施例提供了用于制造诸如finFET的场效应晶体管的改进方法。 应力区域用于增加载流子迁移率。 然而，诸如沉积可流动氧化物和退火的后续过程可能损害应力区域，减少了所引起的应力量。 本发明的实施例在可流动的氧化物沉积和退火之前在应力区域上提供硅或氧化硅的保护层。

公开(公告)号：US09293586B2

公开(公告)日：2016-03-22

申请号：US13944048

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Richard J. Carter ,  Andy Wei ,  Qi Zhang ,  Sruthi Muralidharan ,  Amy L. Child

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

Abstract translation: 提供了在半导体器件（例如，鳍式场效应晶体管器件）的外延连接区域中实现均匀外延（epi）生长的方法。 具体地说，提供了一种半导体器件，包括形成在衬底上的伪栅极和一组鳍状场效应晶体管（FinFET）; 形成在所述伪栅极和所述一组FinFET中的每一个上的间隔层; 以及形成在衬底中的一组凹部内的外延材料，该组凹陷在去除伪栅极之前的外延阻挡层之前形成。

公开(公告)号：US20150380316A1

公开(公告)日：2015-12-31

申请号：US14319640

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong YU ,  HongLiang SHEN ,  Zhao LUN ,  Zhenyu HU ,  Richard J. Carter

IPC: H01L21/8234 ,  H01L21/306 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.

Abstract translation: 对于浅沟槽隔离和其中具有介电材料的深结构沟槽（例如，可流动的氧化物和HARP氧化物）分别使用两种不同的材料导致用于非平面半导体器件的凸起半导体结构的暴露部分的不均匀高度， 由于材料的蚀刻速率不同。 与凸起结构的暴露部分相邻的不均匀的开口不会使隔离和介电材料凹陷，填充有额外的电介质材料，以形成均匀的一层材料（电介质材料）的顶层，然后可将其均匀地凹入以露出均匀的部分 的凸起结构。

公开(公告)号：US09105478B2

公开(公告)日：2015-08-11

申请号：US14064840

申请日：2013-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Wei ,  Mariappan Hariharaputhiran ,  Dae Geun Yang ,  Dae-Han Choi ,  Xiang Hu ,  Richard J. Carter ,  Akshey Sehgal

IPC: H01L21/302 ,  H01L21/033 ,  G03F1/50

CPC classification number: H01L21/0332 ,  G03F1/50 ,  H01L21/0276 ,  H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/823821 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with fins at tight fin pitches are provided. One method includes, for instance: obtaining an intermediate semiconductor device; growing an epi layer over the substrate; forming a doped layer below the epi layer; depositing a first oxide layer on the epi layer; applying a dielectric material on the first oxide layer; and depositing a lithography stack on the dielectric material. One intermediate semiconductor device includes, for instance: a substrate with at least one n-well region and at least one p-well region; a doped layer over the substrate; an epi layer over the doped layer; a first oxide layer over the epi layer; a dielectric layer over the first oxide layer; and a lithography stack over the dielectric layer.

Abstract translation: 提供了用于以紧密翅片间距形成翅片的半导体器件的装置和方法。 一种方法包括，例如：获得中间半导体器件; 在衬底上生长表层; 在外延层下方形成掺杂层; 在外延层上沉积第一氧化物层; 在第一氧化物层上施加电介质材料; 以及在介电材料上沉积光刻叠层。 一个中间半导体器件包括例如：具有至少一个n阱区和至少一个p阱区的衬底; 衬底上的掺杂层; 掺杂层上的外延层; 在epi层上的第一氧化物层; 第一氧化物层上的介电层; 以及介电层上的光刻叠层。

公开(公告)号：US09093561B2

公开(公告)日：2015-07-28

申请号：US14085906

申请日：2013-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Huang Liu ,  Lun Zhao ,  Richard J. Carter

IPC: H01L21/8238 ,  H01L21/768 ,  H01L21/308 ,  H01L21/84

CPC classification number: H01L21/823857 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76829 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/845 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Circuit fabrication methods are provided which include, for example: providing the circuit structure with at least one gate structure extending over a first region and a second region of a substrate structure, the at least one gate structure including a capping layer; and modifying an etch property of at least a portion of the capping layer of the at least one gate structure, where the modified etch property inhibits etching of the at least one gate structure during a first etch process facilitating fabrication of at least one first transistor in the first region and inhibits etching of the at least one gate structure during a second etch process facilitating fabrication of at least one second transistor in the second region.

Abstract translation: 提供了电路制造方法，其包括例如：为电路结构提供在衬底结构的第一区域和第二区域上延伸的至少一个栅极结构，所述至少一个栅极结构包括封盖层; 以及修改所述至少一个栅极结构的覆盖层的至少一部分的蚀刻特性，其中所述修改的蚀刻性能在第一蚀刻工艺期间禁止蚀刻所述至少一个栅极结构，促进制造至少一个第一晶体管 所述第一区域并且在第二蚀刻工艺期间抑制所述至少一个栅极结构的蚀刻，促进在所述第二区域中制造至少一个第二晶体管。

公开(公告)号：US20150099340A1

公开(公告)日：2015-04-09

申请号：US14049848

申请日：2013-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Hyucksoo Yang ,  Huang Liu ,  Richard J. Carter

IPC: H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66795 ,  H01L21/8238 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.

Abstract translation: 本发明的实施例提供了用于制造诸如finFET的场效应晶体管的改进方法。 应力区域用于增加载流子迁移率。 然而，诸如沉积可流动氧化物和退火的后续过程可能损害应力区域，减少了所引起的应力量。 本发明的实施例在可流动的氧化物沉积和退火之前在应力区域上提供硅或氧化硅的保护层。