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    METHOD OF FORMING A SEMICONDUCTOR DEVICE
    11.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20170069550A1

    公开(公告)日：2017-03-09

    申请号：US14844163

    申请日：2015-09-03

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ran Yan ,  Alban Zaka ,  Pei-Yu Chou

    IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/762 ,  H01L21/311

    CPC classification number: H01L21/823878 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/31055 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092

    Abstract: In a first aspect, the present disclosure provides a method of forming a semiconductor device, including providing an SOI structure comprising a base substrate, a buried insulating material layer formed on the base substrate and an active semiconductor layer formed on the buried insulating structure, forming a germanium-comprising layer on an exposed surface of the active semiconductor layer, forming a trench isolation structure, the trench isolation structure extending through the germanium-comprising layer and the active semiconductor layer, performing an annealing process after the trench isolation structure is formed, the annealing process resulting in an oxide layer disposed on a germanium-comprising active layer which is formed on the buried insulating material layer, and removing the oxide layer for exposing an upper surface of the germanium-comprising active layer.

    Abstract translation: 在第一方面，本公开内容提供了一种形成半导体器件的方法，包括提供SOI结构，其包括基底基板，形成在基底基板上的掩埋绝缘材料层和形成在掩埋绝缘结构上的有源半导体层，形成 在有源半导体层的暴露表面上的含锗层，形成沟槽隔离结构，所述沟槽隔离结构延伸穿过含锗层和有源半导体层，在形成沟槽隔离结构之后进行退火处理， 所述退火工艺导致设置在形成在所述掩埋绝缘材料层上的含锗活性层上的氧化物层，以及去除所述氧化物层以暴露所述含锗活性层的上表面。

    Low thermal budget schemes in semiconductor device fabrication
    12.
    发明授权
    Low thermal budget schemes in semiconductor device fabrication 有权
    半导体器件制造中的低热预算方案

    公开(公告)号：US09396950B2

    公开(公告)日：2016-07-19

    申请号：US14184863

    申请日：2014-02-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer ,  Alban Zaka

    IPC: H01L21/336 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    Abstract: In aspects of the present invention, a method of forming a semiconductor device is disclosed, wherein amorphous regions are formed at an early stage during fabrication and the amorphous regions are conserved during subsequent processing sequences, and an intermediate semiconductor device structure with amorphous regions are provided at an early stage during fabrication. Herein a gate structure is provided over a semiconductor substrate and amorphous regions are formed adjacent the gate structure. Source/drain extension regions or source/drain regions are formed in the amorphous regions. In some illustrative embodiments, fluorine may be implanted into the amorphous regions. After the source/drain extension regions and/or the source/drain regions are formed, a rapid thermal anneal process is performed.

    Abstract translation: 在本发明的方面中，公开了一种形成半导体器件的方法，其中在制造期间的早期形成非晶区域，并且非晶区域在随后的处理序列期间保守，并且提供具有非晶区域的中间半导体器件结构 在制造的早期阶段。 这里，在半导体衬底上提供栅极结构，并且在栅极结构附近形成非晶区。 源极/漏极延伸区域或源极/漏极区域形成在非晶区域中。 在一些说明性实施例中，可以将氟注入到非晶区域中。 在形成源极/漏极延伸区域和/或源极/漏极区域之后，执行快速热退火工艺。

    SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL AND METHOD FOR THE FORMATION THEREOF
    15.
    发明申请
    SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL AND METHOD FOR THE FORMATION THEREOF 有权
    包含非易失性存储单元的半导体结构及其形成方法

    公开(公告)号：US20170047336A1

    公开(公告)日：2017-02-16

    申请号：US14918048

    申请日：2015-10-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Alban Zaka ,  Sven Beyer ,  Tom Herrmann ,  El Mehdi Bazizi

    IPC: H01L27/115 ,  H01L21/28

    CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A semiconductor structure includes a nonvolatile memory cell including a source region, a channel region and a drain region that are provided in a semiconductor material. The channel region includes a first portion adjacent the source region and a second portion between the first portion of the channel region and the drain region. An electrically insulating floating gate is provided over the first portion of the channel region. The nonvolatile memory cell further includes a select gate and a control gate. The first portion of the select gate is provided over the second portion of the channel region. The second portion of the select gate is provided over a portion of the floating gate that is adjacent to the first portion of the select gate. The control gate is provided over the floating gate and adjacent to the second portion of the select gate.

    Abstract translation: 半导体结构包括设置在半导体材料中的包括源极区，沟道区和漏极区的非易失性存储单元。 沟道区域包括邻近源极区域的第一部分和沟道区域的第一部分与漏极区域之间的第二部分。 在沟道区域的第一部分之上提供电绝缘的浮动栅极。 非易失性存储单元还包括选择栅极和控制栅极。 选择栅极的第一部分设置在沟道区域的第二部分上。 选择栅极的第二部分设置在与选择栅极的第一部分相邻的浮置栅极的一部分上。 控制栅极设置在浮动栅极上并且邻近选择栅极的第二部分。

    COMPLEX SEMICONDUCTOR DEVICES OF THE SOI TYPE
    16.
    发明申请
    COMPLEX SEMICONDUCTOR DEVICES OF THE SOI TYPE 有权
    SOI类型的复合半导体器件

    公开(公告)号：US20160300947A1

    公开(公告)日：2016-10-13

    申请号：US14680172

    申请日：2015-04-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ran Yan ,  Alban Zaka ,  Jan Hoentschel

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

    CPC classification number: H01L21/823814 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78639 ,  H01L29/78654

    Abstract: The present disclosure provides, in a first aspect, a semiconductor device including an SOI substrate portion, a gate structure formed on the SOI substrate portion and source and drain regions having respective source and drain height levels, wherein the source and drain height levels are different. The semiconductor device may be formed by forming a gate structure over an SOI substrate portion, recessing the SOI substrate portion at one side of the gate structure so as to form a trench adjacent to the gate structure and forming source and drain regions at opposing sides of the gate structure, one of the source and drain regions being formed in the trench.

    Abstract translation: 本公开在第一方面提供了一种半导体器件，其包括SOI衬底部分，形成在SOI衬底部分上的栅极结构以及具有各自的源极和漏极高度水平的源极和漏极区域，其中源极和漏极高度水平是不同的 。 可以通过在SOI衬底部分上形成栅极结构来形成半导体器件，在栅极结构的一侧凹入SOI衬底部分，以形成与栅极结构相邻的沟槽，并在栅极结构的相对侧形成源极和漏极区域 栅极结构，其中一个源极和漏极区域形成在沟槽中。

    Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface
    19.
    发明授权
    Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surface 有权
    通过提供相对于衬底表面具有适当角度的分级嵌入式应变诱导半导体区域来提高晶体管的性能

    公开(公告)号：US08853752B2

    公开(公告)日：2014-10-07

    申请号：US13661188

    申请日：2012-10-26

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： El Mehdi Bazizi ,  Alban Zaka ,  Gabriela Dilliway ,  Bo Bai

    IPC: H01L29/78

    CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

    Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of an efficient strain-inducing mechanism by using an embedded strain-inducing semiconductor alloy. The strain-inducing semiconductor material may be provided as a graded material with a smooth strain transfer into the neighboring channel region in order to reduce the number of lattice defects and provide enhanced strain conditions, which in turn directly translate into superior transistor performance. The superior architecture of the graded strain-inducing semiconductor material may be accomplished by selecting appropriate process parameters during the selective epitaxial growth process without contributing to additional process complexity.

    Abstract translation: 在复杂的半导体器件中，可以通过使用嵌入式应变诱导半导体合金，在有效的应变诱导机制的基础上形成晶体管。 应变诱导半导体材料可以被提供为具有平滑应变转移到相邻沟道区域中的渐变材料，以便减少晶格缺陷的数量并且提供增强的应变条件，这进而直接转化为优异的晶体管性能。 分级应变诱导半导体材料的优越结构可以通过在选择性外延生长工艺期间选择合适的工艺参数而不造成额外的工艺复杂性来实现。

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