公开(公告)号：US09721834B2

公开(公告)日：2017-08-01

申请号：US15092272

申请日：2016-04-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

公开(公告)号：US09698101B2

公开(公告)日：2017-07-04

申请号：US14839108

申请日：2015-08-28

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Andrew M. Greene ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Charan V. V. S. Surisetty ,  Ruilong Xie

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H01L23/528 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/3205 ,  H01L21/32133 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.

公开(公告)号：US20170125414A1

公开(公告)日：2017-05-04

申请号：US15276060

申请日：2016-09-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/08

Abstract: A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.

公开(公告)号：US20170125299A1

公开(公告)日：2017-05-04

申请号：US15357287

申请日：2016-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Balasubramanian Pranatharthiharan ,  Junli Wang ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/517 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/41791 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.

公开(公告)号：US20170104100A1

公开(公告)日：2017-04-13

申请号：US14879220

申请日：2015-10-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Lars W. Liebmann ,  Injo Ok ,  Balasubramanian Pranatharthiharan ,  Ravikumar Ramachandran ,  Soon-Cheon Seo ,  Charan V.V.S. Surisetty ,  Mickey H. Yu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/32139 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66636 ,  H01L29/66795

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.

公开(公告)号：US20170084500A1

公开(公告)日：2017-03-23

申请号：US15366223

申请日：2016-12-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc

Inventor： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8238 ,  H01L27/092 ,  H01L23/522 ,  H01L29/66

CPC classification number: H01L21/823871 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823864 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

公开(公告)号：US09564372B2

公开(公告)日：2017-02-07

申请号：US14740987

申请日：2015-06-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc

Inventor： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/82 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/417

CPC classification number: H01L21/823871 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823864 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

Abstract translation: 制造双硅化物器件的方法包括：生长用于N型器件的源极和漏极（S / D）区域，在栅极结构上形成保护层，并且在N型器件的S / D区域上生长S / D区域用于P型设备。 第一电介质层被共形沉积，部分被去除以暴露S / D区域。 用于P型器件的暴露的S / D区域被硅化以形成衬垫。 第二电介质层被共形沉积。 在第二电介质层上形成电介质填充物。 接触孔通过第二介电层打开，露出P型器件的衬垫，露出N型器件的保护层。 通过打开保护层来暴露N型器件的S / D区域。 暴露的与栅极结构相邻的S / D区域被硅化以形成用于N型器件的衬垫。 触点形成。

公开(公告)号：US09443738B2

公开(公告)日：2016-09-13

申请号：US14616226

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hui Zang ,  Balasubramanian Pranatharthiharan

IPC: H01L29/78 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L21/76897 ,  H01L29/66545

Abstract: Semiconductor devices and methods for forming the devices with middle of line capacitance reduction in self-aligned contact process flow are provided. One method includes, for instance: obtaining a wafer with at least one source, at least one drain, and at least one sacrificial gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; removing the at least one sacrificial gate; forming at least one gate; and forming at least one small contact over the first contact region and the second contact region. An intermediate semiconductor device is also disclosed.

Abstract translation: 提供了用于形成具有自对准接触工艺流程中线路电容减小的器件的半导体器件和方法。 一种方法包括，例如：获得具有至少一个源，至少一个漏极和至少一个牺牲栅极的晶片; 在所述至少一个源极上形成第一接触区域，以及在所述至少一个漏极上形成第二接触区域; 去除所述至少一个牺牲栅极; 形成至少一个栅极; 以及在所述第一接触区域和所述第二接触区域上形成至少一个小接触。 还公开了一种中间半导体器件。

公开(公告)号：US09418902B2

公开(公告)日：2016-08-16

申请号：US14050661

申请日：2013-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L21/84 ,  H01L21/762 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/32 ,  H01L21/76243 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of isolating a semiconductor fin from an underlying substrate including forming a masking layer around a base portion of the fin, forming spacers on a top portion of the fin above the masking layer, removing the masking layer to expose the base portion of the fin, and converting the base portion of the fin to an isolation region that electrically isolates the fin from the substrate. The base portion of the fin may be converted to an isolation region by oxidizing the base portion of the fin, using for example a thermal oxidation process. While converting the base portion of the fin to an isolation region, the spacers prevent the top portion of the fin from also being converted.

Abstract translation: 一种从下面的衬底隔离半导体鳍片的方法，包括在鳍片的基底部分周围形成掩模层，在掩模层上方的翅片的顶部上形成间隔物，去除掩模层以暴露鳍片的基底部分 ，并且将鳍的基部转换成将鳍与基板电隔离的隔离区。 通过使用例如热氧化工艺，可以通过氧化散热片的基部来将散热片的基部转换成隔离区。 在将翅片的基部转换成隔离区域的同时，间隔物防止鳍的顶部也被转换。

公开(公告)号：US09349598B2

公开(公告)日：2016-05-24

申请号：US14832530

申请日：2015-08-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： David V. Horak ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/28 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/28008 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/785

Abstract: A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.