公开(公告)号：US20150249136A1

公开(公告)日：2015-09-03

申请号：US14195330

申请日：2014-03-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Feng ZHOU ,  Tien-Ying LUO ,  Haiting WANG ,  Padmaja NAGAIAH ,  Jean-Baptiste LALOE ,  Isabelle Pauline FERAIN ,  Yong Meng LEE

IPC: H01L29/40 ,  H01L21/311 ,  H01L29/51

CPC classification number: H01L29/401 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/3247 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66545

Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.

Abstract translation: 提供了一种用于制造半导体器件的改进方法。 该方法包括：在基底上沉积电介质层; 在所述电介质层上沉积第一盖层; 在所述电介质层上沉积蚀刻停止层; 以及在所述蚀刻停止层上沉积虚拟盖层以形成部分栅极结构。 还提供了部分形成的半导体器件。 部分形成的半导体器件包括：衬底; 基底上的电介质层; 介电层上的第一盖层; 介电层上的蚀刻停止层; 以及形成部分栅极结构的蚀刻停止层上的虚设盖层。

公开(公告)号：US20140339612A1

公开(公告)日：2014-11-20

申请号：US13896022

申请日：2013-05-16

Applicant: GlobalFoundries Inc.

Inventor： Ashish Kumar JHA ,  Haiting WANG ,  Meng LUO ,  Yong Meng LEE

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L21/02071 ,  H01L21/28238 ,  H01L21/31144 ,  H01L21/823456 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

Abstract: Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity.

Abstract translation: 公开了将替代金属栅极的长度控制到设计的栅极栅极长度的方法以及所得到的器件。 实施例可以包括从形成空腔的衬底上方去除虚拟栅极，其中腔的侧表面衬有氧化间隔层，并且空腔的底表面衬有栅极氧化物层，保形地形成牺牲氧化物层 衬底和空腔，并且从空腔的底表面和衬底去除牺牲氧化物层，留下衬在腔的侧表面的牺牲氧化物间隔物。

公开(公告)号：US20190013245A1

公开(公告)日：2019-01-10

申请号：US15643940

申请日：2017-07-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar JHA ,  Haiting WANG ,  Wei HONG ,  Wei ZHAO ,  Tae Jeong LEE ,  Zhenyu HU

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02

CPC classification number: H01L29/7855 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/475 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/435 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L2027/11805 ,  H01L2027/11831 ,  H01L2029/7858

Abstract: A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.

公开(公告)号：US20180277440A1

公开(公告)日：2018-09-27

申请号：US15467536

申请日：2017-03-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hong YU ,  Zhenyu HU ,  Haiting WANG

IPC: H01L21/8234 ,  H01L21/033 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/311

Abstract: A method of manufacturing a FinFET structure involves forming gate cuts within a sacrificial gate layer prior to patterning and etching the sacrificial gate layer to form longitudinal sacrificial gate structures. By forming transverse cuts in the sacrificial gate layer before defining the sacrificial gate structures longitudinally, dimensional precision of the gate cuts at lower critical dimensions can be improved.

公开(公告)号：US20180190546A1

公开(公告)日：2018-07-05

申请号：US15393488

申请日：2016-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Haiting WANG

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method for eliminating line voids during RMG processing and the resulting device are provided. Embodiments include forming dummy gates over PFET and NFET regions of a substrate, each dummy gate having spacers at opposite sides, and an ILD filling spaces between spacers; removing dummy gate material from the gates, forming a cavity between each pair of spacers; forming a high-k dielectric layer over the ILD and spacers and in the cavities; forming a metal capping layer over the high-k dielectric layer; forming a first work function metal layer over the metal capping layer; removing the first work function metal layer from the PFET region; forming a second work function metal layer over the metal capping layer in the PFET region and over the first work function metal layer in the NFET region; and forming a metal layer over the second work function metal layer, filling the cavities.

公开(公告)号：US20160225675A1

公开(公告)日：2016-08-04

申请号：US14611769

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping SHEN ,  Min-hwa CHI ,  Xusheng WU ,  Weihua TONG ,  Haiting WANG

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L21/3215 ,  H01L21/285

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28568 ,  H01L21/3215 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract translation: 提供一种形成用于nFET和pFET的RMG多WF层的方法，以及所得到的器件。 实施例包括形成Si翅片; 形成nFET RMG沟槽和pFET RMG沟槽; 在nFET和pFET RMG沟槽中形成第一Ti层; 在pFET RMG沟槽中以0°注入角垂直注入第一Ti层中的N 2; 对N 2注入的第一Ti层退火以在pFET RMG沟槽中形成TiN层; 剥离第一Ti层的未反应的Ti; 在nFET和pFET RMG沟槽中形成第二Ti层; 在0°垂直方向将Al或C注入第二Ti层; 退火Al或C注入的第二Ti层，分别在nFET和pFET RMG沟槽的底部形成TiAl或TiC; 并用Al或W填充nFET和pFET RMG沟槽。