公开(公告)号：US20150325681A1

公开(公告)日：2015-11-12

申请号：US14270824

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Bongki Lee ,  Jin Ping Liu ,  Bharat Krishnan

IPC: H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/32133 ,  H01L29/4966 ,  H01L29/66 ,  H01L29/66477

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method is provided for fabricating an integrated circuit. The method includes forming a first FET trench in a first FET region and a second FET trench in a second FET region of an interlayer dielectric material on a semiconductor substrate, at least partially filling the first and second FET trenches with a work function metal to form a work function metal layer, and at least partially removing a portion of the work function metal layer in the second FET trench. The first FET trench is defined as an NFET trench and the second FET trench is defined as a PFET trench.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，提供了一种用于制造集成电路的方法。 该方法包括在半导体衬底上的层间电介质材料的第二FET区域中的第一FET区域和第二FET沟槽中形成第一FET沟槽，至少部分地用功函数金属填充第一和第二FET沟槽以形成 功函数金属层，并且至少部分去除第二FET沟槽中的功函数金属层的一部分。 第一FET沟槽被定义为NFET沟槽，并且第二FET沟槽被定义为PFET沟槽。

公开(公告)号：US20150228755A1

公开(公告)日：2015-08-13

申请号：US14177800

申请日：2014-02-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Andy Wei ,  Jin Ping Liu ,  Shao Ming Koh ,  Amaury Gendron

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238

CPC classification number: H01L29/6681 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively.

Abstract translation: 提供了具有松散硅和锗翅片的集成电路以及用于制造这种集成电路的方法。 该方法包括形成覆盖晶体硅衬底的晶体硅和锗复合层，其中复合层晶格被放宽。 在复合层中形成翅片，并且在翅片上形成栅极。 翅片的一部分在栅极的相对侧上被去除以形成漏腔和源腔，并且源极和漏极分别形成在源极腔和漏极腔中。

公开(公告)号：US10204991B2

公开(公告)日：2019-02-12

申请号：US15482086

申请日：2017-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Jin Ping Liu ,  Min-hwa Chi

IPC: H01L29/165 ,  H01L29/78 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L29/732

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

公开(公告)号：US09647073B2

公开(公告)日：2017-05-09

申请号：US14526831

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Jin Ping Liu ,  Min-hwa Chi

IPC: H01L21/02 ,  H01L33/00 ,  H01L31/00 ,  H01L29/165 ,  H01L29/78 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7848

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

公开(公告)号：US09406676B2

公开(公告)日：2016-08-02

申请号：US14676165

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Jin Ping Liu

IPC: H01L21/76 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the sacrificial gate structures is removed to define a first opening that exposes a portion of the fin. An etch process is performed through the first opening on the exposed portion of the fin to define a first recess in the fin. The first recess is filled with a dielectric material to define a diffusion break in the fin. A device includes a fin defined in a substrate, a plurality of gates formed above the fin, a plurality of recesses filled with epitaxial material defined in the fin, and a diffusion break defined at least partially in the fin between two of the recesses filled with epitaxial material and extending above the fin.

Abstract translation: 一种方法包括在半导体衬底中形成翅片。 在翅片上形成多个牺牲栅极结构。 去除所选择的牺牲栅极结构之一以限定暴露鳍片的一部分的第一开口。 通过翅片的暴露部分上的第一开口进行蚀刻处理，以限定翅片中的第一凹部。 第一凹部填充有电介质材料以限定散热片中的扩散断裂。 一种装置包括限定在衬底中的翅片，形成在鳍片上方的多个栅极，填充有限定在翅片中的外延材料的多个凹槽以及至少部分地限定在翅片中的两个凹槽之间的扩散断裂， 外延材料并在翅片上方延伸。

公开(公告)号：US09401416B2

公开(公告)日：2016-07-26

申请号：US14560035

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jin Ping Liu ,  Haigou Huang ,  Huang Liu

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/02326 ,  H01L21/31053 ,  H01L21/31111 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

Abstract: A method includes forming at least one fin in a semiconductor substrate. A placeholder gate structure is formed above the fin. The placeholder gate structure includes a placeholder material and a cap structure defined on a top surface of the placeholder material. The cap structure includes a first cap layer disposed above the placeholder material and a second cap layer disposed above the first cap layer. An oxidization process is performed on at least a portion of the second cap layer to form an oxidized region above a remaining portion of the second cap layer. A portion of the oxidized region is removed to expose the remaining portion. The remaining portion of the second cap layer is removed. The first cap layer is removed to expose the placeholder material. The placeholder material is replaced with a conductive material.

Abstract translation: 一种方法包括在半导体衬底中形成至少一个翅片。 在翅片上形成占位符门结构。 占位符门结构包括在占位符材料的顶表面上限定的占位符材料和盖结构。 盖结构包括设置在占位符材料上方的第一盖层和设置在第一盖层上方的第二盖层。 在第二盖层的至少一部分上进行氧化处理，以在第二盖层的剩余部分上方形成氧化区域。 去除氧化区域的一部分以露出剩余部分。 去除第二盖层的剩余部分。 移除第一盖层以露出占位符材料。 占位符材料被导电材料代替。

公开(公告)号：US09147696B2

公开(公告)日：2015-09-29

申请号：US14043243

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing Wan ,  Andy Wei ,  Lun Zhao ,  Dae Geun Yang ,  Jin Ping Liu ,  Tien-Ying Luo ,  Guillaume Bouche ,  Mariappan Hariharaputhiran ,  Churamani Gaire

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

Abstract translation: 提供了用FinFET形成半导体器件的器件和方法。 一种方法包括例如：获得具有衬底和至少一个浅沟槽隔离区域的中间半导体器件; 在中间半导体器件上沉积硬掩模层; 蚀刻硬掩模层以形成至少一个翅片硬掩模; 以及在所述至少一个翅片硬掩模和所述基底的至少一部分上沉积至少一个牺牲栅极结构。 一个中间半导体器件包括例如：具有至少一个浅沟槽隔离区域的衬底; 在衬底上的至少一个翅片硬掩模; 至少一个翅片硬掩模上的至少一个牺牲栅极结构; 设置在所述至少一个牺牲栅极结构上的至少一个间隔物; 以及至少一个pFET区域和至少一个生长到衬底中的nFET区域。

公开(公告)号：US09142640B1

公开(公告)日：2015-09-22

申请号：US14306864

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Xiaodong Yang ,  Yanxiang Liu ,  Jin Ping Liu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

Abstract: A non-planar transistor is fabricated with dummy or sacrificial epitaxy and a structure for subsequent replacement or final epitaxy containment is created around the sacrificial epitaxy. The dummy epitaxy is then removed and replaced with the replacement epitaxy. The containment structure allows for uniform growth of the replacement epitaxy and prevents merger. Where n-type and p-type structures are present, the replacement epitaxy process is performed for each type, while protecting the other type with a mask. Optionally, one of the replacement epitaxies, i.e., the one for n-type or p-type, may be used as the dummy epitaxy, resulting in the need for only one mask.

Abstract translation: 用虚拟或牺牲外延制造非平面晶体管，并且在牺牲外延周围产生用于后续替换或最终外延容纳的结构。 然后去除虚拟外延并用替换外延代替。 容纳结构允许替代外延的均匀生长并且防止合并。 在存在n型和p型结构的情况下，对于每种类型进行替换外延工艺，同时用掩模保护另一种类型。 任选地，替代的外延（即，用于n型或p型的）中的一种可以用作虚拟外延，导致仅需要一个掩模。

公开(公告)号：US09142422B2

公开(公告)日：2015-09-22

申请号：US14070823

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hung-Wei Liu ,  Zhiguo Sun ,  Huang Liu ,  Jin Ping Liu

IPC: H01L21/311 ,  H01L23/58

CPC classification number: H01L23/564 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76826 ,  H01L21/76837 ,  H01L21/823418 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.

Abstract translation: 提供了有助于制造无缺陷半导体结构的方法，其包括例如：提供介电层，该电介质层包括至少一种可消耗材料; 选择性地去除所述电介质层的一部分，其中所述选择性去除部分地消耗所述至少一种可消耗材料的剩余部分，在所述电介质层的剩余部分内留下耗尽区; 并且对所述介质层的所述耗尽区进行处理处理，以用至少一种替代的可消耗材料恢复所述耗尽区，从而有助于制造无缺陷的半导体结构。

公开(公告)号：US09087870B2

公开(公告)日：2015-07-21

申请号：US13904626

申请日：2013-05-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Wei Hua Tong ,  Huang Liu ,  HongLiang Shen ,  Jin Ping Liu ,  Seung Kim

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/3115 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/785

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes etching an enhanced high-aspect-ratio process (eHARP) oxide fill that is disposed in an STI trench between two adjacent fins to form a recessed eHARP oxide fill. The two adjacent fins extend from a bulk semiconductor substrate. A silicon layer is formed overlying the recessed eHARP oxide fill. The silicon layer is converted to a thermal oxide layer to further fill the STI trench with oxide material.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，用于制造集成电路的方法包括蚀刻设置在两个相邻散热片之间的STI沟槽中的增强的高纵横比工艺（eHARP）氧化物填充物，以形成凹陷的eHARP氧化物填充物。 两个相邻的翅片从体半导体衬底延伸。 覆盖凹陷的eHARP氧化物填充物形成硅层。 将硅层转化为热氧化物层，以进一步用氧化物材料填充STI沟槽。