中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.013 seconds)

    IC wafer for identification of circuit dies after dicing
    12.
    发明授权
    IC wafer for identification of circuit dies after dicing 有权

    公开(公告)号：US10700013B2

    公开(公告)日：2020-06-30

    申请号：US15867118

    申请日：2018-01-10

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Wen Liu ,  Sebastian T. Ventrone ,  Adam C. Smith ,  Janice M. Adams ,  Nazmul Habib

    IPC: H01L23/544 ,  H01L21/78 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528

    Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.

    Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias
    16.
    发明授权
    Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias 有权
    将半导体器件嵌入到通过硅通孔连接的绝缘体上硅晶片中

    公开(公告)号：US09412736B2

    公开(公告)日：2016-08-09

    申请号：US14296812

    申请日：2014-06-05

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Yan Ding ,  Vibhor Jain ,  Thomas Kessler ,  Yves T. Ngu ,  Robert M. Rassel ,  Sebastian T. Ventrone

    IPC: H01L21/30 ,  H01L27/06 ,  H01L23/48 ,  H01L21/768 ,  H01L23/367 ,  H01L21/84 ,  H01L27/12

    CPC classification number: H01L27/0694 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an approach to fabricating a silicon on insulator wafer, one or more semiconductor device elements are implanted and one or more shallow trench isolations are formed on a top surface of a first semiconductor wafer. A first dielectric material layer is deposited over the top surface of the first semiconductor wafer, filling the shallow trench isolations. A dielectric material layer on a bottom surface of a second semiconductor wafer is bonded to a dielectric material layer on the top of the first semiconductor wafer and one or more semiconductor devices are formed on a top surface of the second semiconductor wafer. Then, one or more through silicon vias are created connecting the one or more semiconductor devices on the top surface of the second semiconductor wafer and the one or more semiconductor device elements on the top surface of the first semiconductor wafer.

    Abstract translation: 在制造绝缘体上硅晶片的方法中，注入一个或多个半导体器件元件，并且在第一半导体晶片的顶表面上形成一个或多个浅沟槽隔离。 在第一半导体晶片的顶表面上沉积第一介电材料层，填充浅沟槽隔离物。 在第二半导体晶片的底面上的电介质材料层与第一半导体晶片的顶部的电介质材料层接合，在第二半导体晶片的顶面上形成有一个以上的半导体装置。 然后，产生连接第二半导体晶片的顶表面上的一个或多个半导体器件和第一半导体晶片的顶表面上的一个或多个半导体器件元件的一个或多个穿过硅通孔。

    Integrated micro-peltier cooling components in silicon-on-insulator (SOI) layers
    17.
    发明授权
    Integrated micro-peltier cooling components in silicon-on-insulator (SOI) layers 有权
    在绝缘体上硅（SOI）层中的集成微帕尔图尔冷却组件

    公开(公告)号：US09299590B1

    公开(公告)日：2016-03-29

    申请号：US14743030

    申请日：2015-06-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Richard S. Graf ,  Ezra D. B. Hall ,  Vibhor Jain ,  Jack R. Smith ,  Sebastian T. Ventrone

    IPC: H01L21/66 ,  H01L21/48 ,  H01L21/78 ,  H01L21/768 ,  H01L21/56 ,  H01L23/38 ,  H01L23/367

    CPC classification number: H01L23/38 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Various particular embodiments include a method of forming an integrated circuit (IC) device including: forming at least one thermoelectric cooling device over an upper surface of a handle wafer based upon a known location of an elevated temperature region in the IC device; forming a first oxide layer over the handle wafer covering the thermoelectric cooling device; forming a second oxide layer over a donor silicon wafer to form a donor wafer; bonding the donor wafer to the handle wafer at the first oxide layer and the second oxide layer, such that the second oxide layer contacts the first oxide layer on the handle wafer; and forming at least one semiconductor device over the donor silicon wafer side of the donor wafer, wherein the at least one thermoelectric cooling device is located proximate the at least one semiconductor device.

    Abstract translation: 各种具体实施例包括形成集成电路（IC）装置的方法，包括：基于IC器件中的升高温度区域的已知位置，在处理晶片的上表面上形成至少一个热电冷却装置; 在覆盖所述热电冷却装置的所述处理晶片上形成第一氧化物层; 在供体硅晶片上形成第二氧化物层以形成施主晶片; 在第一氧化物层和第二氧化物层处将施主晶片接合到处理晶片，使得第二氧化物层接触处理晶片上的第一氧化物层; 以及在施主晶片的供体硅晶片侧上形成至少一个半导体器件，其中所述至少一个热电冷却器件位于所述至少一个半导体器件附近。

Patent Agency Ranking