公开(公告)号：US10026687B1

公开(公告)日：2018-07-17

申请号：US15437100

申请日：2017-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Shao Beng Law ,  James Jay McMahon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.

公开(公告)号：US09805972B1

公开(公告)日：2017-10-31

申请号：US15437065

申请日：2017-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Sean Xuan Lin ,  James Jay McMahon ,  Shao Beng Law

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L21/288 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/288 ,  H01L21/76813 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/14 ,  H01L2924/15787

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; an upper wiring layer with one or more wiring structures, located above the first wiring layer; a blocking material which contacts at least one of the wiring structures of the upper wiring layer; a skip via with metallization, the skip via passes through the upper wiring layer and makes contact with the one or more wiring structures of the first wiring layer; and a conductive material in the skip via above the metallization and in a via interconnect above the blocking material.

公开(公告)号：US10573593B2

公开(公告)日：2020-02-25

申请号：US15983168

申请日：2018-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Shao Beng Law ,  James Jay McMahon

IPC: H01L21/4763 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.

公开(公告)号：US10395926B1

公开(公告)日：2019-08-27

申请号：US15954736

申请日：2018-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Minghao Tang ,  Yuping Ren ,  Sean Xuan Lin ,  Shao Beng Law ,  Genevieve Beique ,  Xun Xiang ,  Rui Chen

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: Methods of self-aligned multiple patterning. A mandrel line is formed over a hardmask layer, and forming a block mask is formed over a first portion of the mandrel line that is linearly arranged between respective second portions of the mandrel line. After forming the first block mask, the second portions of the mandrel line are removed with an etching process to cut the mandrel line and expose respective portions of the hardmask layer. A second portion of the mandrel line is covered by the block mask during the etching process to define a mandrel cut in the mandrel line.

公开(公告)号：US20190206718A1

公开(公告)日：2019-07-04

申请号：US15860121

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Shao Beng Law ,  Sunil K. Singh ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/02118 ,  H01L21/02274 ,  H01L21/31058 ,  H01L21/31111 ,  H01L21/76816 ,  H01L21/76828 ,  H01L23/528 ,  H01L23/53295 ,  H01L2221/1047

Abstract: Interconnect structures and methods for forming an interconnect structure. First and second metallization structures are formed in an intralayer dielectric layer. The intralayer dielectric layer is removed to form a cavity with an entrance between the first and second metallization structures. A dielectric layer is deposited on surfaces surrounding the cavity, over the first metallization structure, and over the second metallization structure. A sacrificial material is formed inside the cavity after the dielectric layer is deposited. A cap layer is deposited on the dielectric layer over the first metallization structure, the dielectric layer over the second metallization structure, and the sacrificial material inside the cavity to close the entrance to the cavity. After the cap layer is deposited, the sacrificial material is removed from the cavity. The dielectric layer and cap layer cooperate to encapsulate an air gap inside the cavity.

公开(公告)号：US20190056671A1

公开(公告)日：2019-02-21

申请号：US15681007

申请日：2017-08-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  John Zhang ,  Shao Beng Law ,  Guoxiang Ning ,  Xunyuan Zhang ,  Ruilong Xie

IPC: G03F7/20 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/544 ,  C23C14/22 ,  C23C16/455

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay mark structures and methods of manufacture. The method includes: forming an overlay mark within a layer of a stack of layers; increasing a density of an upper layer of the stack of layers, above the layer, the increased density protecting the overlay mark; and polishing the upper layer or one or more layers above the upper layer of the stack of layers.

公开(公告)号：US10056291B2

公开(公告)日：2018-08-21

申请号：US15360255

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng Law ,  Xunyuan Zhang ,  Frank W. Mont ,  Genevieve Beique ,  Lei Sun

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/027 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/285

CPC classification number: H01L21/76816

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to post spacer self-aligned cut structures and methods of manufacture. The method includes: providing a non-mandrel cut; providing a mandrel cut; forming blocking material on underlying conductive material in the non-mandrel cut and the mandrel cut; forming trenches with the blocking material acting as a blocking mask at the mandrel cut and the non-mandrel cut; and filling the trenches with metallization features such that the metallization features have a tip to tip alignment.

公开(公告)号：US10014297B1

公开(公告)日：2018-07-03

申请号：US15589312

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Wenhui Wang ,  Xunyuan Zhang ,  Ruilong Xie ,  Jia Zeng ,  Xuelian Zhu ,  Min Gyu Sung ,  Shao Beng Law

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/027 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/6681

Abstract: One aspect of the disclosure is directed to a method of forming an integrated circuit structure. The method may include: providing a set of fins over a semiconductor substrate, the set of fins including a plurality of working fins and a plurality of dummy fins, the plurality of dummy fins including a first subset of dummy fins within a pre-defined distance from any of the plurality of working fins, and a second subset of dummy fins beyond the pre-defined distance from any of the plurality of working fins; removing the first subset of dummy fins by an extreme ultraviolet (EUV) lithography technique; and removing at least a portion of the second subset of dummy fins.

公开(公告)号：US10485111B2

公开(公告)日：2019-11-19

申请号：US15647400

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng Law ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  James McMahon ,  Ryan S. Smith ,  Xunyuan Zhang

IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11 ,  H01L21/768

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

公开(公告)号：US20190318927A1

公开(公告)日：2019-10-17

申请号：US15954066

申请日：2018-04-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Xunyuan Zhang ,  Frank W. Mont ,  Shao Beng Law

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02

Abstract: The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.