公开(公告)号：US09741605B2

公开(公告)日：2017-08-22

申请号：US14676633

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76808 ,  H01L21/31144 ,  H01L21/76813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of reducing defects in and improving reliability of Back-End-Of-Line (BEOL) metal fill includes providing a starting metallization structure for semiconductor device(s), the metallization structure including a bottom layer of contact(s) surrounded by a dielectric material. The starting metallization structure further includes an etch-stop layer over the bottom layer, a layer of dielectric material over the etch-stop layer, a first layer of hard mask material over the dielectric layer, a layer of work function hard mask material over the first hard mask layer, a second layer of hard mask material over the work function hard mask layer, via(s) to the first hard mask layer and other via(s) into the etch-stop layer. The method further includes protecting the other via(s) while removing the second hard mask layer and the layer of work function hard mask material, and filling the vias with metal. Protecting the other via(s) may include, prior to the removing, filling the other via(s) with an Energy Removal Film (ERF) up to a top surface of the first hard mask layer, and, after the removing, removing the ERF material.

公开(公告)号：US20170200674A1

公开(公告)日：2017-07-13

申请号：US14993238

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Shesh Mani Pandey

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/321 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/5226 ,  H01L21/02167 ,  H01L21/02271 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: Methodologies and a device for reducing capacitance and improving profile control are provided. Embodiments include forming metal vias in a first dielectric layer; forming a graded interlayer dielectric over the metal vias; forming a metal layer in the graded ILD over one of the metal vias; and forming a hydrogenated amorphous silicon carbon film over the metal layer.

公开(公告)号：US09576894B2

公开(公告)日：2017-02-21

申请号：US14729188

申请日：2015-06-03

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Xusheng Wu ,  Akshey Sehgal ,  Teck Jung Tang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76811 ,  H01L23/53238 ,  H01L23/53295

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个示例中，制造集成电路的方法包括沉积覆盖在用于形成有机层间电介质（OILD）层的半导体衬底上的有机电介质材料。 在OILD层中形成开口，并且在用于形成金属线和/或通孔的开口中沉积导电金属填充物。

公开(公告)号：US09362162B2

公开(公告)日：2016-06-07

申请号：US14459444

申请日：2014-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Teck Jung Tang ,  Mark Alexander Zaleski

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L2221/1047

Abstract: Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s).

Abstract translation: 提供了用于制造用于例如为电路结构提供BEOL互连的层间结构的方法。 该方法包括例如提供层间结构，包括：在衬底结构之上提供未固化的绝缘层; 在未固化的绝缘层上形成能量去除膜; 通过所述能量去除膜形成至少一个开口并且至少部分地延伸到所述未固化的绝缘层中; 并施加能量以固化未固化绝缘层，建立固化绝缘层，并部分分解能量去除膜，在固化绝缘层上形成厚度减小的能量去除膜，包括固化绝缘层的层间结构，以及 施加减小一个开口的纵横比的能量。 在一个实施方案中，未固化的绝缘层包括在施加能量的同时分解部分以进一步改善纵横比的致孔剂。

公开(公告)号：US09142451B2

公开(公告)日：2015-09-22

申请号：US14027479

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Matthew Herrick ,  Teck Jung Tang ,  Dewei Xu

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.

Abstract translation: 提供具有降低的介电常数的层间制造方法和层间结构。 所述方法包括例如：提供具有可蒸发材料的第一未固化绝缘层; 以及在第一未固化绝缘层上设置具有致孔剂的第二未固化绝缘层。 层间结构包括第一绝缘层和第二绝缘层，并且所述方法还包括固化层间结构，在第一绝缘层中留下空气间隙，以及空气间隙大于孔的第二绝缘层中的孔，以及 其中气隙和气孔降低了层间结构的介电常数。

公开(公告)号：US10580684B2

公开(公告)日：2020-03-03

申请号：US15950907

申请日：2018-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin Wallner ,  Katherina Babich ,  Sunil Kumar Singh

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/66

Abstract: A method of forming an SDB that is self-aligned to a dummy gate and the resulting device are provided. Embodiments include providing a plurality of gates over a SOI layer above a BOX layer, each gate having a pair of sidewall spacers and a cap layer, and a raised S/D epitaxial regions over the SOI layer between each gate; removing a gate of the plurality of gates and a portion of the SOI layer exposed by the removing of the gate, and a portion of the BOX layer underneath the SOI layer, the removing forms a trench; forming a liner of a first dielectric material over and along sidewalls of the trench; and filling the trench with a second dielectric material.

公开(公告)号：US09711346B2

公开(公告)日：2017-07-18

申请号：US14807289

申请日：2015-07-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Shesh Mani Pandey

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/283 ,  H01L49/02 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L21/02186 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31051 ,  H01L23/53228 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55

Abstract: A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench.

公开(公告)号：US09691654B1

公开(公告)日：2017-06-27

申请号：US14978650

申请日：2015-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Sohan Singh Mehta ,  Ravi Prakash Srivastava

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76817 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528

Abstract: Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09613909B2

公开(公告)日：2017-04-04

申请号：US14824181

申请日：2015-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Ravi Prakash Srivastava ,  Nicholas Robert Stokes

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2885 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/535

Abstract: Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings. An intermediate semiconductor device is also disclosed.