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    PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES
    11.
    发明申请
    PREVENTION OF FIN EROSION FOR SEMICONDUCTOR DEVICES 有权
    防止半导体器件的腐蚀

    公开(公告)号：US20140124840A1

    公开(公告)日：2014-05-08

    申请号：US13670674

    申请日：2012-11-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

    Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/311

    CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

    Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

    Prevention of fin erosion for semiconductor devices
    15.
    发明授权
    Prevention of fin erosion for semiconductor devices 有权
    防止半导体器件的翅片侵蚀

    公开(公告)号：US09190487B2

    公开(公告)日：2015-11-17

    申请号：US14283409

    申请日：2014-05-21

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

    Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

    Device structure with increased contact area and reduced gate capacitance
    17.
    发明授权
    Device structure with increased contact area and reduced gate capacitance 有权
    器件结构具有增加的接触面积和降低的栅极电容

    公开(公告)号：US09385231B2

    公开(公告)日：2016-07-05

    申请号：US14530796

    申请日：2014-11-02

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/04 ,  H01L29/08 ,  H01L29/165 ,  H01L29/786

    CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7841 ,  H01L29/78618 ,  H01L29/78654

    Abstract: A FET structure including epitaxial source and drain regions includes large contact areas and exhibits both low resistivity and low parasitic gate to source/drain capacitance. The source and drain regions are laterally etched to provide recesses for accommodating low-k dielectric material without compromising the contact area between the source/drain regions and their associated contacts. A high-k dielectric layer is provided between the raised source/drain regions and a gate conductor as well as between the gate conductor and a substrate, such as an ETSOI or PDSOI substrate. The structure is usable in electronic devices such as MOSFET devices.

    Abstract translation: 包括外延源极和漏极区域的FET结构包括大的接触区域，并且具有低电阻率和低的寄生栅极至源极/漏极电容。 源极和漏极区域被横向蚀刻以提供用于容纳低k电介质材料的凹部，而不损害源极/漏极区域及其相关联的接触之间的接触面积。 高K电介质层设置在凸起的源极/漏极区域和栅极导体之间​​以及栅极导体和诸如ETSOI或PDSOI衬底之类的衬底之间。 该结构可用于诸如MOSFET器件的电子器件中。

    FinFET with crystalline insulator
    19.
    发明授权
    FinFET with crystalline insulator 有权
    FinFET结晶绝缘体

    公开(公告)号：US09257536B2

    公开(公告)日：2016-02-09

    申请号：US13867247

    申请日：2013-04-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

    IPC: H01L29/66

    CPC classification number: H01L29/66795

    Abstract: FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region.

    Abstract translation: 公开了FinFET结构和形成方法。 翅片形成在块状基底上。 在散装衬底上形成结晶绝缘体层，翅片从外延氧化物层伸出。 在从结晶绝缘体层突出的翅片周围形成栅极。 通过将结晶绝缘体层上的翅片合并形成翅片合并区域，在源漏区域中形成外延生长的半导体区域。

    Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures
    20.
    发明授权
    Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures 有权
    具有翅片结构的半导体器件，以及形成具有翅片结构的半导体器件的方法

    公开(公告)号：US09219139B2

    公开(公告)日：2015-12-22

    申请号：US14081320

    申请日：2013-11-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/20

    CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/20 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.

    Abstract translation: 一种半导体器件，包括在衬底表面上的至少两个鳍结构和存在于所述至少两个鳍结构上的功能栅结构。 功能栅极结构包括至少一个与至少两个鳍结构的侧壁直接接触的栅极电介质，以及至少一个栅极电介质上的至少一个栅极导体。 栅极结构的侧壁基本上垂直于衬底表面的上表面，其中由栅极结构的侧壁限定的平面和由衬底表面的上表面限定的平面以90°±/ -5°。 外延半导体材料与至少两个翅片结构直接接触。

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