公开(公告)号：US09236309B2

公开(公告)日：2016-01-12

申请号：US14687300

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chanro Park ,  Steven Bentley

IPC: H01L21/20 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/161 ,  H01L29/165

Abstract: Methods of fabricating one or more semiconductor fin structures are provided which include: providing a substrate structure including a first semiconductor material; providing a fin stack(s) above the substrate structure, the fin stack(s) including at least one semiconductor layer, which includes a second semiconductor material; depositing a conformal protective film over the fin stack(s) and the substrate structure; and etching the substrate structure using, at least in part, the fin stack(s) as a mask to facilitate defining the one or more semiconductor fin structures. The conformal protective film protects sidewalls of the at least one semiconductor layer of the fin stack(s) from etching during etching of the substrate structure. As one example, the first semiconductor material may be or include silicon, the second semiconductor material may be or include silicon germanium, and the conformal protective film may be, in one example, silicon nitride.

Abstract translation: 提供制造一个或多个半导体鳍片结构的方法，其包括：提供包括第一半导体材料的衬底结构; 在所述衬底结构上方提供散热片堆叠，所述散热片堆叠包括至少一个包括第二半导体材料的半导体层; 在所述散热片堆叠和所述基板结构上沉积保形膜; 以及使用至少部分地将所述散热片堆叠作为掩模来蚀刻所述衬底结构，以便于限定所述一个或多个半导体鳍片结构。 共形保护膜在蚀刻衬底结构期间保护散热片堆叠的至少一个半导体层的侧壁免受蚀刻。 作为一个示例，第一半导体材料可以是或包括硅，第二半导体材料可以是或包括硅锗，并且在一个示例中，保形膜可以是氮化硅。

公开(公告)号：US20150214369A1

公开(公告)日：2015-07-30

申请号：US14164934

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jody A. Fronheiser ,  Bharat V. Krishnan ,  Murat Kerem Akarvardar ,  Steven Bentley ,  Ajey Poovannummoottil Jacob ,  Jinping Liu

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/167 ,  H01L29/26 ,  H01L29/04 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/26 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: One illustrative device disclosed herein includes a fin defined in a semiconductor substrate having a crystalline structure, wherein at least a sidewall of the fin is positioned substantially in a crystallographic direction of the substrate, a gate structure positioned around the fin, an outermost sidewall spacer positioned adjacent opposite sides of the gate structure, and an epi semiconductor material formed around portions of the fin positioned laterally outside of the outermost sidewall spacers in the source/drain regions of the device, wherein the epi semiconductor material has a substantially uniform thickness along the sidewalls of the fin.

Abstract translation: 本文公开的一种说明性器件包括在具有晶体结构的半导体衬底中限定的鳍，其中鳍的至少一个侧壁基本上位于衬底的100°结晶方向，位于鳍周围的栅极结构， 侧壁间隔物，其位于栅极结构的相对侧附近，以及外延半导体材料，其围绕位于器件的源极/漏极区域中的最外侧壁间隔物横向外侧的翅片周围形成，其中外延半导体材料具有基本上均匀的厚度 沿翅片的侧壁。

公开(公告)号：US10797138B2

公开(公告)日：2020-10-06

申请号：US15947991

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Steven Bentley

IPC: H01L29/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

公开(公告)号：US20200013684A1

公开(公告)日：2020-01-09

申请号：US16538041

申请日：2019-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Soss ,  Steven Bentley

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/768 ,  H01L29/08

Abstract: The present disclosure is directed to various embodiments of a product that includes first and second vertical semiconductor structures for first and second, respectively, vertical transistor devices, and first and second gate structures positioned adjacent the first and second, respectively, vertical semiconductor structures. The product also includes a shared conductive gate plug positioned laterally between the first gate structure and the second gate structure, wherein the shared conductive gate plug is conductively coupled to both the first gate structure and the second gate structure.

公开(公告)号：US10236379B2

公开(公告)日：2019-03-19

申请号：US15593651

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven Bentley ,  Puneet Harischandra Suvarna ,  Julien Frougier ,  Bartlomiej Jan Pawlak

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.

公开(公告)号：US10170617B2

公开(公告)日：2019-01-01

申请号：US15424379

申请日：2017-02-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiseok Kim ,  Hiroaki Niimi ,  Hoon Kim ,  Puneet Harischandra Suvarna ,  Steven Bentley ,  Jody A. Fronheiser

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/36 ,  H01L29/66 ,  H01L29/417

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

公开(公告)号：US20180130895A1

公开(公告)日：2018-05-10

申请号：US15345644

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Steven Bentley ,  Hoon Kim ,  Min Gyu Sung ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/288 ,  H01L21/321

CPC classification number: H01L29/66666 ,  H01L21/288 ,  H01L21/32136 ,  H01L21/823456 ,  H01L21/823487 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L29/7827

Abstract: One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (S/D) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (S/D) regions. A gate insulation layer is formed above the vertically oriented channel semiconductor structures. A conformal layer of conductive gate material is formed above the gate insulation layer. The conformal layer of conductive material is etched to define conductive gate spacers on sidewalls of the vertically oriented channel semiconductor structures. Top source/drain (S/D) regions are formed above the vertically oriented channel semiconductor structures.

公开(公告)号：US20180033789A1

公开(公告)日：2018-02-01

申请号：US15224139

申请日：2016-07-29

Applicant: GLOBALFOUNDRIES INC. ,  International Business Machines Corporation

Inventor： Steven Bentley ,  Kwan-Yong Lim ,  Tenko Yamashita ,  Gauri Karve ,  Sanjay Mehta

IPC: H01L27/092 ,  H01L21/306 ,  H01L21/762 ,  H01L21/266 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/66803

Abstract: We disclose semiconductor devices, comprising a semiconductor substrate comprising a substrate material; and a plurality of fins disposed on the substrate, each fin comprising a lower region comprising the substrate material, a dopant region disposed above the lower region and comprising at least one dopant, and a channel region disposed above the dopant region and comprising a semiconductor material, wherein the channel region comprises less than 1×1018 dopant molecules/cm3, as well as methods, apparatus, and systems for fabricating such semiconductor devices.

公开(公告)号：US09825032B1

公开(公告)日：2017-11-21

申请号：US15360537

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Bipul C. Paul

IPC: H01L21/8234 ,  H01L27/088 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823487 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/41791 ,  H01L29/66545 ,  H01L2029/7858

Abstract: Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of another transistor pair and resulting device are provided. Embodiments include pairs of fins formed on a substrate; a bottom S/D layer patterned on the substrate around the fins; conformal liner layers formed over the substrate; a ILD formed over a liner layer; a metal routing layer formed between the pairs of fins on the liner layer between the first pair and on the bottom S/D layer between at least the second pair, an upper surface formed below the active fin portion; a GAA formed on the dielectric spacer around each fin of the first pair; and a bottom S/D contact xc or a dedicated xc formed on the metal routing layer adjacent to the GAA or through the GAA, respectively.

公开(公告)号：US20160190323A1

公开(公告)日：2016-06-30

申请号：US14676239

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar ,  Steven Bentley

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/161

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract translation: 一种方法包括在半导体衬底上形成至少一个翅片。 在所述散热片和所述基板的暴露的表面部分上形成硅合金材料。 执行热处理以从硅合金材料和翅片限定硅合金翅片，并且从硅合金材料和基底的暴露表面部分限定硅合金表面部分。 半导体器件包括衬底，限定在衬底上的鳍，鳍包括硅合金并且具有基本上垂直的侧壁，以及衬底上的与硅相邻的硅合金表面部分。