公开(公告)号：US06925006B2

公开(公告)日：2005-08-02

申请号：US10724377

申请日：2003-11-28

申请人： Pierre Fazan ,  Serguei Okhonin

发明人： Pierre Fazan ,  Serguei Okhonin

IPC分类号： G01T1/24 ,  G11C11/403 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/786 ,  H01L31/10 ,  G11C16/04

CPC分类号： H01L27/108 ,  G11C11/403 ,  G11C11/404 ,  G11C11/5621 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841 ,  H04N5/3355 ,  Y10S257/905 ,  Y10S257/907 ,  Y10S438/982

摘要： A semiconductor device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

公开(公告)号：US5949117A

公开(公告)日：1999-09-07

申请号：US580459

申请日：1995-12-26

申请人： Gurtej Singh Sandhu ,  Pierre Fazan

发明人： Gurtej Singh Sandhu ,  Pierre Fazan

IPC分类号： H01L29/423 ,  H01L29/788 ,  H01L29/76

CPC分类号： H01L29/7885 ,  H01L29/42324

摘要： In a semiconductor fabrication method for forming a transistor structure upon a semiconductor substrate, a nitride layer is also formed over the semiconductor substrate. A gate oxide layer is formed over a region of the semiconductor substrate. The gate oxide layer has a relatively thinner oxide region over the nitride layer and a relatively thicker oxide region over the substrate adjacent the nitride layer. A transistor gate is formed extending over the relatively thinner oxide region and over the relatively thicker oxide region. The transistor thus formed is therefore asymmetric. A first transistor active region is formed in the vicinity of the relatively thicker oxide region and a second transistor active region is formed in the vicinity of the relatively thinner oxide region. The nitride layer can be formed by rapid thermal nitridization of the semiconductor substrate. The relatively thinner oxide region can be one-half as thick as the relatively thinner oxide region. The surface of the semiconductor substrate can be curved in the vicinity of the drain of the asymmetric transistor in order to permit the momentum of the charge carriers to facilitate penetration of the charge carriers into the gate.

公开(公告)号：US5491356A

公开(公告)日：1996-02-13

申请号：US153124

申请日：1993-11-15

申请人： Charles Dennison ,  Pierre Fazan

发明人： Charles Dennison ,  Pierre Fazan

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10817

摘要： A three dimensional capacitor structure particularly adapted for use as a memory cell capacitor of a DRAM is disclosed. The capacitor structure incorporates the substantially vertical (in relation to the substrate) sides of a plurality of spacers into the storage node capacitor to increase the total area of the storage node capacitor. In the described embodiments of the invention, a first spacer and a second spacer are formed next to the digit lines. The bottom storage node plate is formed on at least the first sides of the spacers to increase area of the storage node. The bottom storage node plate is also formed on the upper surface of the digit line. Additional spacers can also be added to further increase the area of the storage node. A dielectric layer is formed over the first capacitor plate and a second capacitor plate layer is formed over the dielectric layer to complete the structure.

摘要翻译： 公开了一种特别适用于DRAM的存储单元电容器的三维电容器结构。 电容器结构将多个间隔物的基本垂直（相对于衬底）侧面结合到存储节点电容器中，以增加存储节点电容器的总面积。 在本发明的所述实施例中，第一间隔件和第二间隔件形成在数字线的旁边。 底部存储节点板形成在间隔物的至少第一侧上以增加存储节点的面积。 底部存储节点板也形成在数字线的上表面上。 还可以添加附加的间隔物以进一步增加存储节点的面积。 在第一电容器板上形成电介质层，在电介质层上方形成第二电容器板层以完成该结构。

公开(公告)号：US5371701A

公开(公告)日：1994-12-06

申请号：US223477

申请日：1994-04-05

申请人： Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre Fazan ,  Steven D. Cummings

发明人： Ruojia Lee ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre Fazan ,  Steven D. Cummings

IPC分类号： H01L27/108 ,  H01L29/68

CPC分类号： H01L27/10817

摘要： A stacked delta cell (SDC) capacitor using a modified stacked capacitor storage cell fabrication process. The SDC is made up of polysilicon structure, having an inverted deltoid cross section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The addition of the polysilicon structure increases storage capability 120% without enlarging the surface area defined for a normal stacked capacitor cell.

摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠三角形电池（SDC）电容器。 SDC由具有倒三角形横截面的多晶硅结构构成，位于掩埋接触处，并延伸到由多晶硅覆盖的相邻存储节点之间，介电夹在其间。 多晶硅结构的添加增加了存储能力120％，而不会扩大为正常层叠电容器单元限定的表面积。

公开(公告)号：US5368687A

公开(公告)日：1994-11-29

申请号：US31572

申请日：1993-03-15

申请人： Gurtej S. Sandhu ,  Donald L. Westmoreland ,  Pierre Fazan

发明人： Gurtej S. Sandhu ,  Donald L. Westmoreland ,  Pierre Fazan

IPC分类号： C04B35/01 ,  H01L21/311 ,  H01L21/00

CPC分类号： H01L21/31116 ,  C04B35/01 ,  H01L21/31122

摘要： In one aspect of the invention, a semiconductor processing method includes the following steps: a) providing a layer of an insulating inorganic metal oxide material atop a semiconductor wafer; b) subjecting the wafer with exposed insulating inorganic metal oxide material to dry etching conditions using a halogen or pseudohalogen based chemistry to react the insulating inorganic metal oxide material into solid halogenated or pseudohalogenated material; and c) reacting the solid halogenated or pseudohalogenated material with a gaseous organic ligand precursor to form a gaseous metal organic coordination complex incorporating the organic ligand precursor and to form a gaseous halogenated or pseudohalogenated species which are expelled from the wafer. In another aspect, a semiconductor processing method of removing or otherwise cleaning metal from a semiconductor wafer includes the following steps: a) subjecting a semiconductor wafer having exposed metal to a dry halogen or pseudohalogen gas to react the metal into solid halogenated or pseudohalogenated material; and b) reacting the solid halogenated or pseudohalogenated material with a gaseous organic ligand precursor to form a gaseous metal organic coordination complex incorporating the organic ligand precursor and metal, and to form a gaseous halogenated or pseudohalogenated species, the complex and species being expelled from the wafer. Alternately, the metal is directly incorporated with the gaseous organic ligand precursor without previous halogenation.

摘要翻译： 在本发明的一个方面，一种半导体处理方法包括以下步骤：a）在半导体晶片的顶部设置绝缘无机金属氧化物层; b）使用暴露的绝缘无机金属氧化物材料的晶片对干蚀刻条件进行干燥，使用卤素或基于假卤素的化学反应将绝缘无机金属氧化物材料反应成固体卤化或假卤化材料; 和c）使固体卤化或假卤素材料与气态有机配体前体反应，形成掺入有机配体前体的气态金属有机配位络合物，并形成从晶片排出的气态卤化或假卤化物质。 另一方面，从半导体晶片去除或以其他方式清除金属的半导体处理方法包括以下步骤：a）使具有暴露金属的半导体晶片经干卤素或拟卤素气体使金属反应成固体卤化或假卤素材料; 和b）使固体卤化或假卤素材料与气态有机配体前体反应，形成结合有机配体前体和金属的气态金属有机配位络合物，并形成气态卤化或假卤化物质，复合物和物质从 晶圆。 或者，金属直接与气态有机配体前体结合，而无需先前的卤化。

公开(公告)号：US5358894A

公开(公告)日：1994-10-25

申请号：US175481

申请日：1993-12-30

申请人： Pierre Fazan ,  Viju Mathews ,  Gurtej S. Sandhu ,  Mohammed Anjum ,  Hiang C. Chan

发明人： Pierre Fazan ,  Viju Mathews ,  Gurtej S. Sandhu ,  Mohammed Anjum ,  Hiang C. Chan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02238 ,  H01L21/02299 ,  H01L21/31662 ,  H01L21/76213 ,  Y10S148/116 ,  Y10S148/163

摘要： A LOCOS process is enhanced by enhancing the depth of field oxide in regions having a narrow field oxide width. Subsequent to forming a pattern of nitride to define the field oxide and active area, photoresist is applied to selected areas of the wafer. An impurity is then applied to the underlying semiconductor substrate in areas not protected by photoresist and nitride. The impurity results in an enhanced oxidation rate and therefore compensates for a thinning effect in selected field oxide areas, such as those having a narrow width. Subsequent formation of the field oxide results in the doped material being consumed by the oxide.

摘要翻译： 通过在具有窄场氧化物宽度的区域中增强场氧化物来增强LOCOS工艺。 在形成氮化物图案以限定场氧化物和有源区域之后，将光致抗蚀剂施加到晶片的选定区域。 然后在不受光致抗蚀剂和氮化物保护的区域中将杂质施加到下面的半导体衬底。 杂质导致增强的氧化速率，因此补偿了选择的场氧化物区域（例如具有窄宽度的区域）中的稀化效应。 随后形成场氧化物导致掺杂材料被氧化物消耗。

公开(公告)号：US5262343A

公开(公告)日：1993-11-16

申请号：US852822

申请日：1992-03-06

申请人： Howard E. Rhodes ,  Pierre Fazan ,  Hiang C. Chan ,  Charles H. Dennison ,  Yauh-Ching Liu

发明人： Howard E. Rhodes ,  Pierre Fazan ,  Hiang C. Chan ,  Charles H. Dennison ,  Yauh-Ching Liu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/70

CPC分类号： H01L27/10852 ,  H01L28/40

摘要： This invention relates to semiconductor circuit memory storage devices and more particularly to a process to develop three-dimensional stacked capacitor cells using a high dielectric constant material as a storage cell dielectric and a combination of conductively doped polysilicon and metal silicide as the capacitor plates of a storage cell for use in high-density dynamic random access memory (DRAM) arrays. The present invention teaches how to fabricate three-dimensional stacked capacitors by modifying an existing stacked capacitor fabrication process to construct the three-dimensional stacked capacitor cell incorporating a high dielectric constant material as the cell dielectric that will allow denser storage cell fabrication with minimal increases of overall memory array dimensions. A capacitance gain of 3 to 10.times. or more over that of a conventional 3-dimensional storage cell is gained by using a high dielectric constant material as the storage cell dielectric.

摘要翻译： 本发明涉及半导体电路存储器存储器件，更具体地说，涉及使用高介电常数材料作为存储单元电介质和导电掺杂多晶硅和金属硅化物的组合来开发三维叠层电容器单元的方法，作为电容器板 用于高密度动态随机存取存储器（DRAM）阵列的存储单元。 本发明教导了如何通过修改现有的层叠电容器制造工艺来制造三维层叠电容器，以构建结合有高介电常数材料的三维叠层电容器单元作为电池电介质，其将使得更密集的存储单元制造以最小的增加 整体内存阵列尺寸。 通过使用高介电常数材料作为存储单元电介质，获得比常规3维存储单元的电容增益高3至10倍或更多的电容增益。

公开(公告)号：US5236860A

公开(公告)日：1993-08-17

申请号：US799461

申请日：1991-11-26

申请人： Pierre Fazan ,  Gurtej S. Sandhu ,  Hiang C. Chan ,  Yauh-Ching Liu

发明人： Pierre Fazan ,  Gurtej S. Sandhu ,  Hiang C. Chan ,  Yauh-Ching Liu

IPC分类号： H01L27/108

CPC分类号： H01L27/10817

摘要： A lateral extension stacked capacitor (LESC) using a modified stacked capacitor storage cell fabrication process. The LESC is made up of polysilicon structure, having a spherical ended v-shaped cross-section. The storage node plate of the LESC is overlaid by polysilicon with a dielectric sandwiched in between and connects to an access device's active area via a buried contact. The plate extends to an adjacent storage node but is isolated from the adjacent node by less than the critical resolution dimension of a given lithographic technology. The addition of the polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell.

摘要翻译： 一种侧向延伸堆叠电容器（LESC），采用改进的堆叠电容器存储单元制造工艺。 LESC由多晶硅结构组成，具有球形末端的V形横截面。 LESC的存储节点板由介质夹在其间的多晶硅覆盖，并通过埋入触点连接到接入设备的有源区。 板延伸到相邻的存储节点，但是通过小于给定光刻技术的临界分辨率尺寸与相邻节点隔离。 多晶硅结构的添加增加了存储能力50％，而不会扩大为正常埋地数字线叠层电容器电池定义的表面积。

公开(公告)号：US5137842A

公开(公告)日：1992-08-11

申请号：US699291

申请日：1991-05-10

申请人： Hiang C. Chan ,  Pierre Fazan

发明人： Hiang C. Chan ,  Pierre Fazan

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91

摘要： An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked H-Cell (SHC). The SHC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SHC is made up of a polysilicon storage node structure having a H-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SHC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an H-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.

摘要翻译： 修改现有的堆叠电容器制造工艺以构建称为堆叠H电池（SHC）的三维叠层电容器。 SHC设计定义了在本发明中用于DRAM处理的电容器存储单元。 SHC由具有H形横截面上部的多晶硅存储节点结构构成，下部向下延伸并通过埋入触点与有源区接触。 多晶硅存储节点结构由多晶硅覆盖，电介质夹在其间以形成完整的SHC电容器。 具有H形横截面的新颖的三维多晶硅储存节点板允许在存储节点处获得大于常规STC的电容器板表面积为200％或更大的电容器板表面积。

公开(公告)号：US5061650A

公开(公告)日：1991-10-29

申请号：US643835

申请日：1991-01-17

申请人： Charles H. Dennison ,  Hiang Chan ,  Yauh-Ching Liu ,  Pierre Fazan ,  Howard E. Rhodes

发明人： Charles H. Dennison ,  Hiang Chan ,  Yauh-Ching Liu ,  Pierre Fazan ,  Howard E. Rhodes

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L28/91 ,  H01L27/10817

摘要： A method is disclosed for forming a capacitor on a semiconductor wafer. A first electrically conductive layer is applied atop the wafer and engages exposed active areas. A first dielectric layer is next applied. The first dielectric and conductive layers are then patterned to define an outline for the lower capacitor plate. A second dielectric layer, having an etch rate which is slower than the first, is then applied and planarized or otherwise etched down to the first dielectric layer. The first dielectric layer is then etched down to the first conductive layer to produce upwardly projecting walls of second dielectric material surrounding the lower capacitor plate outline. A second electrically conductive layer is then applied. It is then anisotropically etched to provide a first electrically conductive wall extending upwardly from the first conductive layer. A third dielectric layer is then applied. The third dielectric layer is then anisotropicallly etched to provide a first dielectric wall extending upwardly from the first conductive layer adjacent the first conductive wall. A third electrically conductive layer is next applied over the first conductive and dielectric walls. It is then anisotropically etched to provide a second electrically conductive wall extending upwardly from the first conductive layer adjacent the first dielectric wall. The first dielectric wall is then etched from the wafer. A capacitor dielectric layer is then applied, followed by a fourth electrically conductive layer to form an upper capacitor plate.

摘要翻译： 公开了一种在半导体晶片上形成电容器的方法。 将第一导电层施加在晶片顶部并接合暴露的有源区。 接下来应用第一电介质层。 然后将第一介电层和导电层图案化以限定下电容器板的轮廓。 然后施加具有比第一介质层慢的蚀刻速率的第二介电层，并将其平坦化或以其它方式蚀刻到第一介电层。 然后将第一电介质层向下蚀刻到第一导电层，以产生围绕较低电容器板轮廓的第二介电材料的向上突出的壁。 然后施加第二导电层。 然后对其进行各向异性蚀刻以提供从第一导电层向上延伸的第一导电壁。 然后施加第三介电层。 然后对第三电介质层进行各向异性蚀刻以提供从邻近第一导电壁的第一导电层向上延伸的第一电介质壁。 接着将第三导电层施加在第一导电和电介质壁上。 然后对其进行各向异性蚀刻以提供从邻近第一介电壁的第一导电层向上延伸的第二导电壁。 然后从晶片蚀刻第一电介质壁。 然后施加电容器介电层，随后是第四导电层以形成上电容器板。